JPH0115217B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an interface return test method for circuits installed in digital telephones, basic home control equipment, non-telephone home equipment, etc., and used for interface formation. It is something.

(b) Background of the Technology The configuration of a digital telephone from an exchange to a terminal is schematically shown in FIG. 1 or 2. 1st
The figure shows the case where the terminal is a telephone, FIG. 2 shows the case where the terminal is a non-telephone home appliance, etc., and FIG. 6 shows the frame structure of the signal between the interfaces in FIGS. 1 and 2. In Fig. 6, F is a flag, B is data that is actually sent (audio data or terminal data), and D is a bit that performs control. show. If the device is a phone, the first
As shown in the figure, a digital telephone (DTEL) 11 is connected from a digital switch (TD) 13 via a line termination unit (DSU) 12 through a 64 kb/s or 16 kb/s channel. At this time, the interface circuit section 1 is connected between the telephone 11 and the DSU 12.
4 is provided. If the terminal is a non-telephone home device, etc., the digital exchange 13 is
Basic home control device (B-
TCE) 22, and from the B-TCE 22 to non-telephone home equipment, etc. 21. DSU12 and B
- TCE22 is connected by a 64kb/s or 16kb/s channel. B-TCE22 has DSU
One interface circuit section 14a is provided as an interface to 12, and another interface circuit section 14b is provided as an interface to non-telephone household equipment 21. The non-telephone home equipment 21 also has an interface circuit section 14 as an interface to the B-TCE 22.
c is provided. The above-mentioned interface circuit section 1
4a and 14c are used as the transmitter/receiver for the DSU12 and B-TCE, and work in slave mode.
4b is used as a transmitting/receiving unit for the B-TCE terminal 21 and functions as a master mode, and although the mode of use is different, the same device can be used. Note that slave mode refers to the interface of lower-level devices such as digital telephones, non-telephones, and B-TCE interfaces seen from the DSU.
The master mode is the opposite of the slave mode, and indicates an interface provided on the higher-level device side. This configuration is shown in FIG.

FIG. 3 shows the configuration of the interface circuit section. In the figure, a frame separation unit 31 inputs a communication line (CMI) signal and divides it into an information signal, that is, a 64 kb/s data signal, and a control signal, that is,
The control signals are separated into 16 kb/s call control signals and stored in the microprocessor interface section 32. The frame assembling section 33 extracts data from the interface section 32, combines it with an information signal, and outputs the assembled frame as a CMI signal. A digital phase lock loop section 34 generates a clock A synchronized with the received signal, and inputs the output to a clock B when in slave mode. In master mode, an external clock unrelated to clock A is input.

In the CMI signal in Figure 3, the logic signal "0"
is represented by a signal that changes from low level (L) to high level (H) at the midpoint of the bit, and is a logic signal "1".
is represented by a signal that alternates between low and high. A specific example is shown in FIG. That is, FIG. 4 1 shows the data displayed as a logic signal "0" or "1", FIG. 4 2 shows the NRZ signal corresponding to the data, and FIG. 4 3 shows the CMI signal corresponding to the data. Signals are written side by side.

In addition to the above-mentioned signals, the CMI signal also includes a violation (frame synchronization signal) in the frame assembly unit 3.
is added for each frame of the signal. Violation is the logic “1” that appeared before it.
This is indicated by maintaining the same level as the signal for one bit period. The section indicated by the arrow in the CMI signal in FIG. 4 is a violation.

However, at present, no method has been established for testing the interface section of a communication line.

(c) Purpose of the Invention The present invention takes into account the drawbacks of the prior art and provides a method that allows for easy testing of the interface section of a communication line.

(d) Structure of the Invention According to the present invention, a frame decomposition unit receives a communication line signal and decomposes it into an information signal and a control signal, and a microprocessor stores data decomposed by the frame decomposition unit. A processor interface, a circuit that generates a clock to be applied to the frame disassembly unit in synchronization with the received signal, and a frame is assembled by inputting the control signal and information signal of the microprocessor interface and used as a communication line signal. A communication line interface circuit comprising a frame assembling section for transmitting data includes a feedback circuit that feeds back from an output of the frame assembling section to an input of the frame disassembling section, and a microprocessor interface provided before the frame disassembling section. A first selection circuit that selects the received communication line signal or the feedback output according to the command of and a second circuit that grounds the input of the circuit that generates the clock when loopback testing is performed in slave mode.
This is achieved by providing a communication line interface part loopback test method characterized in that a third selection circuit is provided and the loopback test is performed in master/slave mode.

(e) Embodiments of the invention Hereinafter, embodiments of the present invention will be described in detail with reference to FIG.

In the embodiment of FIG. 5, the same symbols as in FIG. 3 indicate the same parts as in FIG. In FIG. 5, the selection circuit 36 applies feedback from the output of the frame assembling section 33 to the input stage of the frame separation section 31 via the flip-flop circuit 35, and selects either the received signal or the feedback signal and sends it to the frame separation section 31. supply This selection is made by a mode selection command from the microprocessor interface 32. In addition, selection circuits 37 and 38
selects whether to ground the input of the clock pulse generation circuit or apply the received signal. This is done by the master-slave switching signal and the mode selection command 32.The master-slave switching switch sets the selection circuit 37 so that it is on the solid line side in the master mode, and applies the received signal to the circuit 34. , the selection circuit 38 is connected to the dotted line side (ground side) in the test mode. In slave mode, the generated clock A is input to clock B and the interface is synchronized with the received signal.
When the circuits 37 and 38 are connected by dotted lines, the circuit 34 runs free. The selection circuit 38 is used to make the circuit 34 run free during slave mode testing.

Further, when the selection circuit 36 is connected with a solid line, the received signal is applied to the frame separation section 31, but when the interface section 32 commands the test mode, the data of the interface section 32 is applied to the frame assembly section 31.
3. The data signal which is sent to the frame separation section 31 via the circuit 36 and is its separated output is returned to the interface section and tested to see if there are any errors in the data. In this way, selection circuit 3 during testing
8 to ground is to connect the clock output from circuit 34 again to circuit 3 by looping it back for testing.
This is to prevent synchronized pull-in from being impossible due to pull-in to 4. Flip-flop circuit 35
is used for waveform compensation in the feedback circuit.

(f) Effects of the Invention As explained in detail above, according to the present invention, by adding an extremely simple loopback circuit and selection circuit, it is possible to conduct a loopback test of an interface in master-slave mode. The present invention is extremely effective in testing interfaces installed in digital telephones, basic home control devices, non-telephone home equipment, and the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating the relationship between a digital telephone and a digital exchange for explaining the background technology of the present invention, FIG. 2 is a block diagram illustrating the relationship between non-telephone home equipment and a digital exchange, and FIG.
The figure is a block diagram of the conventional interface section in Figures 1 and 2, and Figure 4 is a block diagram of the conventional interface section in Figures 1 and 2.
A waveform diagram showing an example, FIG. 5 is a block diagram of an interface section according to the method according to the present invention, and FIGS. 6 and 7 show the frame structure of the signal and the structure of the interface in FIGS. 1 and 2. FIG. 35...Flip-flop circuit, 36, 37,
38...Selection circuit.

Claims (1)

[Claims] 1 A frame decomposition unit that receives a communication line signal and decomposes it into an information signal and a control signal, a microprocessor interface that stores the data decomposed by the frame decomposition unit, and a frame decomposition unit that stores the data decomposed by the frame decomposition unit, and decomposes the frame in synchronization with the received signal. and a frame assembling section that inputs control signals and information signals from the microprocessor interface to assemble a frame and transmit it as a communication line signal. a feedback circuit that feeds back the output of the assembling section to the input of the frame disassembling section; and a feedback circuit that is provided before the frame disassembling section and selects the feedback output from a communication line signal received in response to a command from the microprocessor interface. 1 selection circuit and a circuit that generates the clock, and inputs the received signal to the circuit that generates the clock when in the master/slave mode, and generates the clock when performing a loopback test in the slave mode. A loopback test method for a communication line interface section, characterized in that second and third selection circuits are provided to ground the input of the circuit, and the loopback test is performed in master/slave mode.