JPH01155281A - Logic test circuit - Google Patents

Abstract

PURPOSE:To perform a logic circuit test by a method wherein an output of a delay circuit for which an initial value can be set is inverted logically and a logically inverted output is supplied, being switched from a data input signal, to the input of the delay circuit through a switch which is controllable from outside. CONSTITUTION:Only an ordinary input signal from a data input terminal 1, a clock signal from a clock input terminal 2 and a reset signal from an initial value setting input terminal 3 are taken to the input of a delay circuit 5. A delay input in relation to the ordinary input signal is switched from an output of the delay circuit 5 through an inverter circuit 6 and a selector switch 7. In other words, the switch 7 selects a data input 1 as a data input to the delay circuit 5 in an ordinary state, while selecting a signal obtained by inverting an output logic of the delay circuit 5, as the data input of this circuit. A logic circuit test can be performed by controlling the switch 7 directly from an external terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic test circuits, and more particularly to cooking test circuits that support sequential circuits.

[Conventional technology]

Conventionally, this type of logic test circuit tests the logic circuit by inputting a test pattern from the outside.

FIG. 3 is a logic test circuit for explaining a conventional example.

As shown in FIG. 3, such a test circuit has an inverter circuit 6 and a Nant gate 10a to
The normal input signal from the data input terminal 1 is transferred to the test data input terminal 9 through a gate circuit switch consisting of 10c and 10c.
The circuit configuration is such that a test pattern is applied to the delay circuit 5 during testing, and delayed data is output to the data output terminal 4. Note that the delay circuit 5 has a clock (CK) input terminal 2 and an initial value setting (R).
An input terminal 3 is connected to the gate circuit switch, and a test system (gI signal input terminal 8) is connected to the gate circuit switch.

[Problem that the invention seeks to solve]

In the conventional buried test circuit described above, if the circuit has many delay circuits, the number of test pattern input terminals to each delay circuit will increase, and therefore the number of wiring will increase, and a large number of external test patterns will be required. There were drawbacks.

An object of the present invention is to provide a logic test circuit that does not require such an external test pattern and has a reduced number of input terminals.

[Means for deciding the issue]

The logic test circuit of the present invention includes a delay circuit in which an initial value can be set by inputting data and a clock and one or more delay circuits are connected in cascade, a circuit for logically inverting the output of the delay circuit as a sequential circuit, and a circuit for logically inverting the output of the delay circuit as a sequential circuit. It has a changeover switch that switches the output of the inversion circuit with a data input signal and supplies it to the input of the delay circuit, and is configured to control the changeover switch directly from an external terminal.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a logic test circuit diagram for explaining a first embodiment of the present invention.

a clock signal from clock input terminal 2;
The configuration is such that only the reset signal from the initial value setting input terminal 3 is taken in, and the delay input for the normal input signal is switched from the output of the delay circuit 5 via the inverter circuit 6 and the changeover switch 7.

That is, in the normal state, the selector switch 7 selects the data input 1 as the data input of the delay circuit 5, while in the test state, the selector switch 7 selects the data output logic of the delay circuit 5 as the data input of the delay circuit 5. Faith reversed! Select. Therefore, in the test state, the delay circuit 5
operates as a counter circuit that counts clock signals. The delay circuit 5, which operates as a counter circuit, generates a test pattern as a logic signal "1010" alternately and automatically in synchronization with a clock signal.

In short, the one-delay circuit 5 does not function as a test pattern generation source, and the test control signal, its terminal, and test data input terminal for generating the test pattern are also no longer required.

FIG. 2 is a logic test circuit diagram for explaining a second embodiment of the present invention. - As shown in FIG. 2, the test circuit of this embodiment has a circuit configuration in which the delay circuit 5 of the first embodiment described above is arranged vertically in two stages, and the other circuits and terminals are the same as those of the first embodiment. Example circuit,
Same as terminal.

With this configuration, the number of switches and signal lines is reduced compared to when a switch is provided for each delay circuit, and the additional portion as a test circuit becomes smaller. Further, during testing, the logic signal generated from the delay circuit which has become a counter circuit is 11001100', which becomes a source for automatically generating a test pattern different from that of the first embodiment described above.

〔Effect of the invention〕

As explained above, the logic test circuit of the present invention can generate test patterns automatically inside the logic circuit without using test patterns from the outside by simply adding some hardware to a normal circuit. This has the effect of significantly reducing the number of input terminals and automating logic circuit testing. *Reducing the number of input terminals has a great effect on semiconductor integrated circuits that have a limited number of terminals.

[Brief explanation of the drawing]

Fig. 1 is a logic test circuit diagram for explaining the first embodiment of the present invention, Fig. 2 is a logic test circuit diagram for explaining the second embodiment of the invention, and Fig. 3 is a conventional logic test circuit diagram. Here is a logic test to explain an example. l...Data input terminal, 2...Clock input terminal, 3...Initial value setting input terminal, 4...
...Data output terminal, 5.5m, 5b...
・Delay circuit, 6... Inverter circuit, 7...
···switch.

Claims (1)

[Claims] In a logic test circuit having a sequential circuit, a delay circuit that receives data and a clock and can set an initial value in which one or more delay circuits are vertically connected, and a circuit that logically inverts the output of the delay circuit as a sequential circuit; A logic test circuit comprising a changeover switch that switches the output of the logic inversion circuit to a data input signal and supplies the signal to the input of the delay circuit, and the changeover switch described in appendix is controlled directly from an external terminal.