JPH01161459A - Bus debugger device - Google Patents

Abstract

PURPOSE:To remarkably facilitate the simulation and the monitor of the signal of a bus by allowing a memory to store the movement of the signal of the bus with the aid of a sequensor, reading the data of the memory to the outside and monitoring it when the request of the bus is simulated with the aid of a microprocessor. CONSTITUTION:The microprocessor 1 controlled by the program of a local memory 9 executes access for the data bus part 4 and the address bus part 5 of an exclusive bus in an exclusive bus cycle through an interface 6 and simulates the request of the leased bus. On the other hand, the movement of the signal of the data bus part 4 and the address bus part 5 of the exclusive bus is stored in a First In and First Out system in the memory group 7 by the sequence 8. Therefore, when the data of the memory group 7 is successively read by returning to the old one and simultaneously displayed on an external display device through an input/output mechanism 10 or printed out, the movement of the exclusive bus can be recognized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus debugger device that monitors a computer bus.

(Prior Art) To monitor a computer bus, it is necessary to observe signals exchanged with devices and to apply an appropriate voltage to the bus. Conventionally, signals were observed by connecting a logic analyzer to a bus bin, often a backboard bin, and observing the trigger-like waveform.

Also, to give the appropriate voltage to the bus, is it direct current? It was done statically by connecting the anode on the shore or connecting it to the ground point.

[Problem that the invention seeks to solve]

Since the number of channels of the above-mentioned conventional logic analyzer used for bus monitoring is much smaller than the number of signal lines of the bus, there is a problem in that the same operation must be repeated many times.

Another problem is that it is not possible to dynamically simulate changes in bus signals, making it impossible to test the bus slave alone.

The present invention was made in order to solve the above problems, and aims to provide a bus debugger device that can easily simulate and monitor bus signals, and can also test a single bus slave. purpose.

[Means for solving problems]

A bus debugger device according to the present invention includes a microprocessor that can send signals to a bus, a memory that can be accessed from both the microprocessor and the bus, and a sequencer that stores the movement of signals on the bus in the memory. It is prepared.

(Function) In this invention, a bus request is simulated by a microprocessor, the movement of this bus signal is stored in a memory, and the data in this memory is read out to the outside for monitoring. Simulating and monitoring bus signal behavior is significantly facilitated, and testing of individual pass slaves is also possible.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. In the figure, (1) is a general-purpose microprocessor, (2) is the data bus of this microprocessor, (3) is the address bus of this microprocessor, and (4) is the data bus section of the dedicated path of the computer to be debugged. ,(5
) is the address bus part of this dedicated bus, (6) is the data bus part (2) and address bus (3) of the microprocessor (1), and the data bus part (4) and address bus part (5) of the dedicated bus. The interface (7) provided between the dedicated bus and the microprocessor (1)
A memory group that can be accessed from both (
8) is a sequencer controlled by cycles of a dedicated bus,
(9) is a local memory accessed only by the microprocessor (1), and (10) is the input/output mechanism of the microprocessor (1). Note that these devices are attached to a single card of the size of the dedicated bus so that they can be directly mounted in the slot of the dedicated bus.

The operation of this embodiment configured as described above will be explained below.

A microprocessor (1) controlled by a program in a local memory (9) runs a data bus section (
4) and address bus section (5), to the interface (
6) to access in a dedicated path cycle and simulate a dedicated bus request.

On the other hand, the movement of signals in the data bus section (4) and address bus section (5) of the dedicated bus is controlled by the sequencer (8) as follows: First In, First 0.
ut) method in the memory group (7).

Therefore, using the microprocessor (1), the data in the memory group (7) is read out in order from the oldest to the oldest, and the data is displayed on an external display device or printed out via the input/output mechanism (10). You can understand the movements of private buses by looking at the following information.

Since these devices are installed on a single card the size of a dedicated bus, handling is very convenient, and since this device uses a general-purpose microprocessor, its control program can be run easily. It can be accumulated as an asset.

In the above embodiment, the microprocessor bus and the dedicated bus are both separated into addresses and data, which is the so-called separated bus monitoring. However, the present invention is not limited to this. Even with a shared bus, the same simulation and monitoring as described above is possible through protocol control.

(Effects of the Invention) As is clear from the above explanation, according to the present invention, when a bus request is simulated by a microprocessor, the sequencer stores the movement of signals on the bus in memory, and stores the data in this memory. Since it can be read out and monitored externally, bus signal simulation and control are greatly facilitated, and furthermore, it is possible to test a single pass slave.

[Brief explanation of the drawing]

The figure is a block diagram showing the configuration of an embodiment of the present invention. (1): Microprocessor (4): Data bus section of dedicated bus (5): Address bus section of dedicated bus (7): Memory group (8): Sequencer (9): Local memory

Claims (1)

[Claims] A bus debugger device for simulating and monitoring the movement of signals transmitted on a bus, comprising: a microprocessor that sends signals to the bus; a memory that can be accessed by both the microprocessor and the bus; a sequencer for storing signal movements in the memory, and simulating requests on the bus by the microprocessor;
A bus debugger device characterized in that the sequencer causes the movement of signals on the bus to be stored in the memory, and the data in the memory is read out to the outside for monitoring.