JPH01162015A - Electric field effect transistor logic circuit - Google Patents

Abstract

PURPOSE:To cause a logical amplitude to be wide, to obtain a high speed and to enlarge a noise margin without especially complexing a manufacture procedure by discharging a gate charge in the normally-on type FET (EFET) for driver of a DCFL like a direct current with the EFET of a coupling circuit. CONSTITUTION:When an input signal Vin to be supplied to an input terminal 21 is a potential Vih of an H, a charging current Ih is flown from the input terminal 21 to a node A and a potential Va of the node A rises up. As a result, as long as the H potential Vih of the input signal Vin is Vih<2Vf, neither the parasitic diodes a diode 31 nor an EFET23 is turned on and clamp effect is not generated. Accordingly, the logical amplitude can be made wide and the noise margin can be enlarged. On the other hand, when the input signal Vin is changed from the H potential Vih to an L potential Vil, a discharging current Il is flown from the node A to the input terminal 21. Accordingly, when a potential Va is slightly higher than the input signal Vin, an EFET32 is turned on and the discharging current Il like the direct current is made to flow.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention is constructed using a Schottky junction field effect transistor, a PN junction field effect transistor, etc. formed on a compound semiconductor substrate such as GaA3. The present invention relates to field effect transistor logic circuits.

(Prior Art) In recent years, Ga8 integrated circuits, which have the characteristics of ultra-high speed and low power consumption, have attracted attention.

As a logic circuit for product circuits, DCF L (Direct Coupled F
ieldeffect transistor Logi
A variety of field effect transistor (hereinafter referred to as FET) logic circuits called c) have been proposed.

Conventionally, this type of FET logic circuit was developed in Japanese Patent Application Laid-Open No. 1986-
There was one described in Publication No. 231920. below,
Its configuration will be explained using figures.

FIG. 2 is a circuit diagram showing an example of the configuration of a conventional DCFL type FE and T logic circuit.

This FET logic circuit has input terminal 1 for input signal vin.
, output signal V. , 1, a normally-off type FET (hereinafter referred to as EFET) 3 for the driver, and a normally-on type FET (hereinafter referred to as DFET) 4 for the load, and these EFETs 3 and DFET 4 are connected to the
connected in series between the potential vdd and the ground GND,
Input terminal 1 is roughly connected to the gate of EFET 3, and output terminal 2 is commonly connected to the drain of EFET 3 and the gate and case of DFET 4.

This FET logic circuit outputs an output signal V which is an inversion of the input signal vio. , t.

In this type of circuit, EFET3 and DFET4 are configured with Schottky junction FETs or PN junction FETs, and parasitic diodes exist between the gate and source and between the gate and train. Therefore, if the voltage (Vi,) applied to the gate of EFET3 is even slightly higher than the turn-on voltage of the parasitic diode, a diode forward current will flow from the gate of EFET3 to the source, and the potential of the input signal Vin has a clamping effect that cannot be higher than this turn-on voltage vf. Here, the turn-on voltage Vf of the parasitic diode is
Schottky junction type FETr 0.6 to 0.8V, PN
Since the junction type FET is about 1■, the logic amplitude of this FET logic circuit is less than 1■, and the MO3 of the Si integrated circuit is
It has the disadvantage that it is extremely small compared to circuits, etc., and has a small noise margin. Further, the current due to the clamp effect causes unnecessary power consumption, which has been an obstacle to reducing power consumption.

As an example of a circuit that eliminates the drawbacks of such FET logic circuits, there is an FET logic circuit as shown in FIG. 3 described in the above-mentioned document.

This FET logic circuit has input terminals 1 and E in FIG.
A coupling circuit 10 is connected between the gate of FET3. This coupling circuit 10 is composed of a pair of diodes 11 and 12 connected in antiparallel. here,
One diode 11 is for increasing the logic amplitude, and has a forward polarity when the input signal Vio is at a high level (hereinafter referred to as "'H"), and connects the input terminal 1 and EF.
connected between the gate of ET3 and the other diode 1
2 is connected with the opposite polarity to the diode 11 in order to discharge the gate charge of the EFET 3.

In this FET logic circuit, when the input signal Vio supplied to the input terminal 1 is "H", the signal vi.

is divided and applied to the diode 11 and EFET 3. Therefore, the turn-on voltage of diode 11 is set to EFE.
If f is the same as the parasitic diode of T3, then EFET3
Since the gate potential of Vio is Vin/2, the input signal Vio
The clamping effect does not occur until Vf exceeds 2Vf (V). As a result, the 4L HII of the input signal Vio can be increased, the logic amplitude can be increased, and the noise margin can also be increased. Further, if the power supply voltage Vdd is set to 2Vf (V) or less, no clamping effect occurs, so that power consumption can be reduced. On the other hand, is the input signal 75 V i p high?
When it changes from + to “B”, the diode 12 causes E
The gate charge of FET3 is discharged relatively quickly.

Therefore, the circuit shown in FIG. 3 has the advantages of large logic amplitude, high noise margin, low power consumption, and high-speed logic operation.

(Problems to be Solved by the Invention) However, the FET logic circuit shown in FIG. 3 has the following problems.

In the circuit shown in FIG. 3, when the input signal Vio changes from "HTl" to "BI'", the diode 11 becomes reverse biased, so the DC discharge path of the gate charge of EFET 3 is connected to the diode 12 side which is the forward direction. Become. However, in terms of direct current, when the gate potential of EFET 3 becomes lower than the turn-on voltage Vf of the diode 12,
Since it is in the off state, discharge current no longer flows. That is,
The gate potential of the EFET 3 does not fall below Vf in terms of direct current, and only the alternating current component is discharged by the open coupling circuit formed by the diodes 11 and 12. Therefore, when the input signal Vio is "V", the impedance of the gate of EFET3 is high at O(V) to vf, which is effective as the input voltage of the DCF1 circuit, and it is easy for noise to occur, and the gate potential increases due to the noise. If this happens, there is a problem in that there is no direct current path for gate charge discharge, so charges remain and malfunction occurs.

In order to solve these problems and obtain a logic amplitude with a large serration similar to that in Fig. 3, a diode 12
It requires a difficult manufacturing process technique to make the turn-on voltage Vj as small as O(V), and the polarity direction is forward from the input terminal 1 to the EFET 3.
That is, it is necessary to connect a large number of diodes in series in the same direction as the polarity of the diode 11, and as a result, the number of elements increases, and high-speed performance is impaired by the increase in the number of stages of diodes.

Further, the above problem can be solved by reducing only the Vf of the diode 12, but even in such a solution, it is necessary to form an element with a large vf such as an EFET including the diode 11 and a parasitic diode. Apart from the manufacturing process, there is a problem in that a complicated manufacturing process and advanced technology are required to form the diode 12 with a small vf.

The present invention solves the problem that the prior art had, in order to prevent the logic amplitude from decreasing due to the clamping of the parasitic diode in the driver EFET 3.
When a coupling circuit 10 consisting of 1.12 is provided, its EF
The present invention provides an FET logic circuit that solves the problems of the gate of ET3 being discharged only in an alternating current manner and being susceptible to noise, and the manufacturing process becoming complicated if it were to be made strong against noise.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention has a load EFET to which a power supply voltage is applied, and a driver DFET connected to this EFET. In an FET logic circuit in which an input signal is supplied to the gate of the driver EFET through a coupling circuit, the coupling circuit is connected in series with a polarity such that the direction of current flowing from at least the input terminal toward the gate is a forward direction. one or more diodes connected to the diode, and a channel provided in parallel with the diode and serving as a drain or source, one of which is connected to the input terminal, and the other end of which is connected to the gate of the driver EFET together with the gate. It is composed of EFET.

(Function) According to the present invention, since the FET logic circuit is configured as described above, the diode in the coupling circuit works to expand the logic amplitude, and the EFET functions as a driver EFET.
It works to discharge the gate charge of . As a result, the gate potential of the driver EFET can be stabilized against noise without complicating the manufacturing process compared to conventional circuits, and the logic amplitude can be expanded, noise margin improved, and power consumption reduced. and high-speed performance.

Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a circuit diagram of a FET logic circuit showing an embodiment of the present invention.

This FET logic circuit is formed on a compound semiconductor substrate such as GaAS, and has an input terminal 2 for input signal Vi1.
1. Output signal v. , an output terminal 22 for the driver, an EFET 23 for the driver, a DFET 24 for the load, and a coupling circuit 3
0, the EFET 23 and DFET 24 are connected in series between the ground GND and the power supply voltage Vdd, the drain of the EFET 23 and the gate and source of the DFET 24 are commonly connected to the output terminal 22, and the DCF
An L circuit inverter is configured.

A coupling circuit 30 is connected between the gate of the EFET 23 and the input terminal 21.

The coupling circuit 30 includes a diode 31 for expanding logic amplitude,
E for discharging the gate charge of EFET23 in a direct current manner
FET32. The diode 31 is connected between the input terminal 21 and the node with a forward polarity in the direction from the input terminal 21 to the gate side node of the EFET 23, and the turn-on voltage of the diode 31 is equal to the parasitic voltage in EF[T23. The voltage value is set to be approximately the same as the turn-on voltage Vf of the diode. EFET3
2, one of both ends of the channel serving as the drain or source is connected to the input terminal 21, and the other side is connected to the EFE together with the gate.
They are respectively connected to the gate side node A of T23. In addition, ■h in FIG. 1 is the charging current, 1. l! is the discharge current.

In the above configuration, the basic operation of the circuit shown in FIG. 1 will be explained first, and then it will be explained that the logic amplitude can be increased in the circuit shown in FIG. 1 without impairing high-speed performance.

First, an input signal Vi is supplied to the input terminal 21.

When the potential vih is H'', a charging current Ih flows from the input terminal 21 toward the node A, and the potential v8 of the node A rises.Due to the direction of the current, the input terminal 21 side of the EFET 32 becomes the drain at this time, and the Since the A side becomes the source, the voltage between the gate and the source becomes O (V), and the device is in an off state.

Therefore, charging of the gate of the EFET 23 is performed in an alternating current manner, and the input signal Vio is divided in inverse proportion to the ratio of the capacitance C1 between the two terminals of the coupling circuit 30 and the capacitance C2 of the gate of the EFET 23. Ru. For example, capacitances C1 and C2
If they are equal, a voltage of Vi, /2 will be applied to the gates of the coupling circuit 30 and the EFET 23, respectively,
As a result, the diode 31 and E
None of the parasitic diodes of FET 23 turn on and no clamping effect occurs. Therefore, increase the logic amplitude,
It becomes possible to increase the noise margin.

On the other hand, the input signal ■in changes from t Hu potential Vih to
When the potential changes to Vig, a discharge current IJ2 flows from the node A toward the input terminal 21. At this time, due to the direction of the current, the input terminal 21 side of the EFET 32 of the coupling circuit 30 becomes the source, and the node A side becomes the drain, and the gate potential and drain potential are both equal to the potential Va of the node A, so the potential ■ becomes Input signal ■IO from EFET
If the threshold voltage Vt is higher than 32, the EFET
32 is turned on. The EFET 32 of the coupling circuit 30 may be formed at the same time as the driver EFET 23, and the threshold voltage Vt of the EFET is set to E in the general manufacturing process of the DCFL circuit.
Since it is set to a positive voltage value of about O(V), which is sufficiently small compared to the turn-on voltage Vf of the parasitic diode of the FET, the EFET
Set the threshold voltage Vt of 32 to Vt=O and Vt>O.
It can be done. Therefore, if the potential V is even slightly higher than the input signal io, the EFET 32 is turned on and the DC discharge current 1. ! will flow.

FIG. 4 shows the potential Va of the node A when the input signal Vin changes from the potential Vih to the potential Vig.
E which shows the relationship between and the discharge current ■ρ flowing through EFET32
It is a characteristic curve diagram of FET32.

In FIG. 4, the potential va does not exceed Vf due to the parasitic diode of EFET 23, so the input signal ■
When H'' of in is 2Vf, the initial state of the potential Va is Vf, and since vin>Va, the EFET 32 is in the off state. As the potential of the input signal Vin decreases,
When va=-vf, as mentioned above, <EFET
32 turns on, a discharge current begins to flow DC along the curve L1 in Fig. 4, and the potential va becomes equal to the input signal @V.
i falls to a potential equal to g. Roughly input signal ■
As io decreases, the characteristic curve in Figure 4 moves to the left, and the input signal vio reaches the potential ■i,! When it reaches , the characteristic curve becomes a curve LO, and the potential va decreases to a potential equal to viJ2. Due to the characteristics of DCFL, the potential Viρ is O
(V), and the charge at the gate of EFET23 is that potential.
2, it is discharged with direct current. Therefore, the gate charge of the EFET 23 is discharged faster than in a conventional circuit in which discharge is performed only in an alternating current manner by a diode.

Next, the influence of noise on the circuit shown in FIG. 1 will be explained.

As mentioned above, when the input signal vio is at the low potential Viρ
When this happens, a positive pulse noise is applied to the gate of EFET 23 and the potential Va becomes higher than the input signal ■io, EFET 32 is turned on and the charge on the gate of EFET 23 is quickly discharged, and the potential va becomes Recover. That is, if the input signal io is "BI°", the input terminal 21 and the gate of the EFET 23 are coupled in a direct current manner, so that the manufacturing process can be made without complicating the manufacturing process as described above.
You can obtain something that is resistant to positive pulse noise.

On the other hand, when the input signal vin is “Hfl”, EFET3
2 is in an off state with respect to the direction of the charging current Ifi, so if a negative pulse noise is applied to the gate of EFET 23 and the potential va decreases, the potential 8 will not recover and the voltage shown in FIG. The circuit configuration alone is not necessarily strong against negative pulse noise. However, if the power supply voltage Vdd is set to 2Vf or more and the clamping effect occurs when the input signal @V i 1 is j (H11), a product that is strong against negative pulse noise can be obtained. Although there is a problem that unnecessary power consumption occurs due to current, by adopting the following circuit configuration, it is possible to obtain a device that does not consume power due to clamp current and is resistant to negative pulse noise. It becomes possible.

That is, in the circuit of FIG. 1, the capacitance N of the coupling circuit 30
C1 is set smaller than the capacitance C2 of the gate of EFET 23, and the power supply voltage Vdd is set higher than the voltage at which the diode 31 is turned on and lower than the voltage at which the parasitic diode of the EFET 23 is turned on.

For example, when C1=02/2, the forward voltage Vb (=Vi
FIG. 5 shows the relationship between the voltage (Va) and the gate voltage (Va) of the EFET 23.

FIG. 5 is a characteristic diagram of the voltages va and vb in FIG. 1, in which B1 indicates the turn-on point of the diode 31, and B2 indicates the turn-on point of the EFET 32, respectively.

As mentioned above, the input signal ■io is divided in inverse proportion to the capacitance ratio, so Va=1/3・Vio, Vb=2/3
・When the potential of the input signal vin increases due to Vin,
Diode 31 turns on first at point 81. At this time, Vb=Vf, Va=1/2・Vf, Vi,=3/
Even if Vio increases after reaching 2.Vf, the diode 3
The voltage ■b of 1 becomes constant, and only the voltage ■b increases. Roughly speaking, when ■in=2Vf, the parasitic diode of EFET 23 is also turned on. Therefore, the power supply voltage is 3/2・V
If f < Vdd < 2V [, the diode 3
Only EFET 1 turns on, and the parasitic diode of EFET23 does not turn on, so the input signal ■in becomes u HI+
If so, even if a negative pulse noise is applied to the gate of the EFET 23, the gate of the EEET 23 is charged through the diode 31, and its potential (8) is restored. Also, EFE
Since the parasitic diode of T23 is not turned on,
No clamp current flows and no power is wasted.

Further, the DC input/output transfer characteristic of the FET logic circuit shown in FIG. 1 has a hysteresis characteristic as shown in FIG. For example, as in the above configuration, let C1=C2/2, and D
If the sense level V of the inverters of EFET 23 and DFET 24, which are equivalent to the CFL circuit, is designed to be Vf/2, as mentioned above, when the input signal vin changes from ``L'' to ``H'', the potential va becomes Vf/2. Naru na wa Vin
= Vf, and at this time the output signal V. ut becomes 'B'. That is, it HI + sense level Vhs of the entire circuit is vh,=Vf. On the other hand, the input signal v
When i0 drops from "Hll" to "B'," there is no discharge path in terms of DC, and EFET 32L is turned on when vlo<Va+vto#Va.

Note that vto is the threshold voltage of the EFET 32. As mentioned above, at this time, the initial states of Vio and ■8 are approximately 2Vf and V', respectively, and Va remains unchanged until Vio becomes less than vf, and from then on, va decreases in almost the same relationship as vio. Therefore, when the input signal \/10 becomes Vf/2, the potential Va also becomes Vf/2, and the output signal V. is V, I!3=vf/2, and vF S <Vhs, showing a hysteresis characteristic as shown in FIG.

As described above, the circuit shown in FIG. 1 not only has a large logic amplitude width but also has hysteresis characteristics, so that the noise margin is significantly improved.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(i) Although the inverter circuit has been described in the above embodiment, the present invention can also be applied to other DCF1 circuits such as a NOR circuit, a NAND circuit, and a flip-flop circuit. EFE
A coupling circuit 3 consisting of a diode 31 and an EFET 32 is connected between the T and a plurality of input terminals provided correspondingly.
By connecting 0 to each, the same effect as the circuit shown in FIG. 1 can be obtained.

(ii) The coupling circuit 30 of FIG. 1 does not need to have only one stage of diodes 31; a large number of diodes may be connected in series so that their polarities are in the same direction; Even in a configuration in which an impedance element that does not block the DC component is inserted and connected in series on the path, substantially the same effect as in the above embodiment can be obtained.

(Effects of the Invention) As explained in detail above, according to the present invention, the DCFL
Since the discharge of the gate charge in the driver EFET is made to be DC discharged by the EFET of the coupling circuit, the logic amplitude can be increased compared to the conventional circuit without complicating the manufacturing process. It is large and fast, and enables stable logic operation that is resistant to positive pulse noise. In addition, for products with high power supply voltage,
In addition to positive pulse noise, it is also resistant to negative pulse noise. By making the capacitance of the coupling circuit smaller than the gate capacitance of the driver EFET, it is possible to obtain an operating power supply voltage range that is strong against both positive and negative pulse noise and operates without wasting power due to clamp current. This makes it possible to significantly reduce power consumption with a power supply voltage within this range. In addition to expanding the logic amplitude, the DC transfer characteristic has hysteresis, so the noise margin can be significantly increased.

Therefore, it can be applied to various fields that require noise resistance, such as input/output circuits such as compound semiconductor integrated circuits and interface circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a FET logic circuit showing an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams of a conventional FET logic circuit,
4 is a characteristic curve diagram of the EFET 32 of FIG. 1, FIG. 5 is a characteristic diagram of the voltages Va and Vb of FIG. 1, and FIG. 6 is a DC transfer characteristic diagram of FIG. 1. 23...EFET for driver, 24...
・Load DFET, 30...Coupling circuit, 31・
...Diode, 32--EFET.

Claims (1)

[Claims] 1. A normally-on field-effect transistor for a load to which a power supply voltage is applied, and a normally-off field-effect transistor for a driver connected to this field-effect transistor, and input from an input terminal. In a field effect transistor logic circuit in which an input signal is supplied to the gate of the normally-off field effect transistor for driver through a coupling circuit, the coupling circuit is configured such that the direction of current flowing from the input terminal toward the gate is in the forward direction. one or more diodes connected in series in terms of polarity; one end of a channel provided in parallel with the diode and serving as a drain or source is connected to the input terminal, and the other end is connected to the gate together with a normally-off field effect for the driver; A field effect transistor logic circuit comprising: a normally-off field effect transistor connected to a gate of the transistor. 2. The capacitance of the coupling circuit is smaller than the capacitance of the gate of the normally-off field effect transistor for the driver, and the power supply voltage is such that the diode turns on when the input signal is at a high level. 2. The field effect transistor logic circuit according to claim 1, wherein the field effect transistor logic circuit is set to a voltage value that is sufficiently large for the driver and is smaller than that at which a parasitic diode in the driver normally-off field effect transistor is turned on.