JPH01165247U - - Google Patents
Info
- Publication number
- JPH01165247U JPH01165247U JP1988061387U JP6138788U JPH01165247U JP H01165247 U JPH01165247 U JP H01165247U JP 1988061387 U JP1988061387 U JP 1988061387U JP 6138788 U JP6138788 U JP 6138788U JP H01165247 U JPH01165247 U JP H01165247U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- printing elements
- connection pad
- insulating substrate
- measurement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Electronic Switches (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988061387U JPH0711984Y2 (ja) | 1988-05-10 | 1988-05-10 | 印字ヘッド |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988061387U JPH0711984Y2 (ja) | 1988-05-10 | 1988-05-10 | 印字ヘッド |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01165247U true JPH01165247U (it) | 1989-11-17 |
| JPH0711984Y2 JPH0711984Y2 (ja) | 1995-03-22 |
Family
ID=31287059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988061387U Expired - Lifetime JPH0711984Y2 (ja) | 1988-05-10 | 1988-05-10 | 印字ヘッド |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0711984Y2 (it) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH048556A (ja) * | 1990-04-26 | 1992-01-13 | Matsushita Electric Ind Co Ltd | サーマルヘッドおよびその抵抗値トリミング法 |
| JP2001301219A (ja) * | 2000-04-19 | 2001-10-30 | Rohm Co Ltd | サーマルプリントヘッド |
-
1988
- 1988-05-10 JP JP1988061387U patent/JPH0711984Y2/ja not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH048556A (ja) * | 1990-04-26 | 1992-01-13 | Matsushita Electric Ind Co Ltd | サーマルヘッドおよびその抵抗値トリミング法 |
| JP2001301219A (ja) * | 2000-04-19 | 2001-10-30 | Rohm Co Ltd | サーマルプリントヘッド |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0711984Y2 (ja) | 1995-03-22 |
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