JPH01171274A - Manufacturing method of thin film transistor - Google Patents

Abstract

PURPOSE:To simplify manufacturing steps by forming an N-type gate electrode directly on a semiconductor film for the gate electrode so as to implant more N-type impurity than P-type impurity and indirectly a P-type source.drain regions through a gate oxide film by continuously ion-implanting two types of different impurities. CONSTITUTION:A gate oxide film 3 is formed on an active layer 3, an Si semiconductor film 4 is then formed, only the film 4 is patterned, and the film 3 remains as it is. B<+> is, for example, implanted as a P-type impurity under the condition of 3X10<15>/cm<2> of dose, and As<+> is, for example, subsequently implanted as an N-type impurity under the condition of 5X10<15>/cm<2> of dose. The B<+> is selectively implanted to a part which becomes the source.drain region of an active layer 2 by the continuous implanting, thereby forming source.drain region 7 on the layer 2. The B<+> implanted previously is compensated by the As<+> implanted later in the film 4 to reduce an N-type resistance. As a result, an N-type gate electrode 4' is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved method for manufacturing a CMOS type thin film transistor having both N and P channel transistors on the same insulating substrate.

Traditionally, CMOS type thin film transistors are generally made of N and P transistors on the same insulating substrate 1, such as a glass plate, as shown in Figure 1.
Poly-3 in the part that becomes each channel transistor
A Si semiconductor active layer 2 such as i, a-5i (amorphous Si) is formed [Fig. 1 (2)], and its surface is thermally oxidized to form a gate oxide film 3 of SiO2 [Fig. A Si semiconductor film 4 for gate electrode is formed on the entire surface [Fig.
], N-type impurities are diffused into this film by a coating diffusion method or a vapor phase diffusion method to lower the resistance [Fig. Figure 1 ■]
, continue with the ion implantation method (arrow 6) while leaving the resist 5.
The active layer 2 is formed through the gate oxide film 3 by ion implantation).
A P-channel transistor source/drain region 7 is formed by doping P-type impurities into the [first
Figure ■], After removing the resist, dope the other transistor with N-type impurities by using ion implantation method (arrow 6' indicates ion implantation) with one transistor entirely masked with resist. The gate electrode 4# and the source/drain region 7' of the N-channel transistor are formed by [Fig. 1 ■], and the whole is then treated and activated in an oxidizing atmosphere [Fig. It is manufactured by forming a SiO□ interlayer insulating film, a contact hole, and a metal electrode such as AΩ.

The purpose of the present invention is to reduce the resistance of the Si semiconductor film during the formation of the N-type gate electrode and to form the source and drain regions of the P-channel transistor by continuous ion implantation, thereby simplifying the manufacturing process of the CMOS type. An object of the present invention is to provide a method for manufacturing a thin film transistor.

In the method of the present invention, after sequentially forming the Si semiconductor active layer of both N and P channel transistors, the -SiO□ gate oxide film, and the Si semiconductor film for the gate electrode on the same insulating substrate,
Type gate electrode and P channel transistor source
In a method for manufacturing a CMOS thin film transistor including steps of sequentially forming drain regions, forming an N-type gate electrode and forming P-channel source/drain regions,
In the former case, it is added directly to the semiconductor film for the gate electrode so that the gate electrode contains more N-type impurities than P-type impurities, and in the latter case, it is added to the source/drain regions of the active layer through the gate oxide film. This method is characterized in that it is performed indirectly by sequential ion implantation of two different types of impurities.

In this way, the method of the present invention can reduce the resistance of the Si semiconductor layer using N-type impurities when forming an N-type gate electrode (hereinafter referred to as N-type resistance reduction), and form the source/drain regions using P-type impurities in a P-channel transistor. This method simplifies the process by continuously performing the steps by ion implantation.

The method of the present invention will be explained in detail according to the process diagram shown in Fig. 2. First, SL semiconductors such as poly-3i are deposited on the same insulating substrate 1 such as a glass plate at portions that will become N and P channel transistors by low pressure CVD. method (e.g. SiH4 flow rate 40
sccM, vacuum degree of 0.5 torr, and temperature of 630° C.), etc., to a thickness of about 2,000 mm.
After forming the semiconductor active film, patterning is performed by photolithography and etching to form a Si semiconductor active layer 2 [FIG. 2 (2)]. Subsequently, a gate oxide film 3 made of SiO□ with a thickness of approximately 1,500 wafers is formed on the surface of the active layer 2 by thermal oxidation [see FIG. Furthermore, an SL semiconductor such as poly-5i, which will become a gate electrode, is deposited on the entire surface by CVD or the like to a thickness of about 4000 nm, as in the case of the active layer, to form a Si semiconductor film 4 [FIG. 2 (2)]. Conventionally, the N-type resistance of the Si semiconductor film 4 was reduced by a coating diffusion method or a vapor phase diffusion method at this point, but in the present invention, patterning is directly performed by a photolithography etching method. Si
Only the semiconductor film 4 is left, and the gate oxide film 3 is left as is.

After removing the resist [FIG. 2 (4)], continuous ion implantation, which is a feature of the present invention, is performed. First, use B1 as a P-type impurity at an energy of 60 eV and a dose of 3.
XIO"/ai, and then as an N-type impurity, for example, As" is implanted at an energy of 50 KeV and a dose of 5 x 10"/aJ. Through this continuous implantation, the source/drain regions of the active layer 2 and As a result, Bo is selectively injected into the portion where the source becomes (As” is the source
It is blocked by the SiO2 film on the drain region. )
Source/drain regions 7 are formed in the active layer 2, while
Both Bo and As2 are implanted into the Si semiconductor M4, and the dose of these impurities is As'')B as described above.
”, the B injected earlier in the Si semiconductor film 4
+ is compensated by As' implanted later and becomes N-type with low resistance, resulting in formation of N-type gate electrode 4'(6.6' is continuous ion implantation of B'''' and As'')
[Fig.
sb", p" can be used. The thickness of the gate oxide film is preferably in the range of 200 to 4,000 thick in the portions that will become the source and drain regions. Of course, the order of implanting the impurities may be reversed. In addition, the impurity dose may be any value as long as it satisfies the conditions of N-type impurity>P-type impurity, but usually the N-type impurity dose is lXl0''~IX
IO”/at(, P-type impurity dose t5 Xl014~
5 Xl0is/d(7)iH"C".

After that, P was
Only the channel transistor region is masked with a resist 5', and an N-type impurity, for example, phosphorus, is implanted into the N-channel transistor region again under conditions of an energy of 150 KeV and a dose of 5.times.10@1 s/d. Through this ion implantation, both B3 and Po are implanted into the portion that will become the source/drain region 7' of the N-channel transistor, but under the same conditions as above (the dose amount is N).
If implantation is performed with type impurity>P type impurity), B9 will be compensated for Po and become N type.

In addition, Po enters the gate electrode 4'' of the N-channel transistor, but since this part has already been made into an N-type low resistance, the resistance becomes even lower (6'' is P9 ion implantation) [Fig.

Thereafter, as in the conventional method, after activation in an oxidizing atmosphere (thermal oxidation) [Fig.

The process of the present invention is completed by forming an interlayer insulating film, contact holes, and metal (usually AQ) electrodes.

- As described above, the method for manufacturing a CMO8-type O8 transistor of the present invention includes reducing the N-type resistance of the 81 semiconductor film when forming an N-type gate electrode, and forming source/drain regions using P-type impurities in a P-channel transistor. Since this is performed continuously by ion implantation, the process can be simplified compared to the conventional method.

[Brief explanation of the drawing]

FIGS. 1 and 2 are manufacturing process diagrams of an example of a conventional CMo5 type thin film transistor and an example of the present invention CMo5 thin film transistor, respectively. 1... Insulating substrate 2... Si semiconductor active layer 3...
・Gate oxide film 4...Si semiconductor film 4.4#...
・Gate electrode 5, 5'... resistor, 6',
6"...Ion implantation 7.7'...Source/drain region Fig. 1

Claims (1)

[Claims] 1. After sequentially forming the Si semiconductor active layer of both N- and P-channel transistors, the SiO_2 gate oxide film, and the Si semiconductor film for gate electrode on the same insulating substrate, the source/drain regions of the N-type gate electrode and P-channel transistor are formed. In a method for manufacturing a CMOS thin film transistor that includes sequential formation steps, forming an N-type gate electrode and forming a P-channel source/drain region, in the former case, the gate electrode contains more N-type impurities than P-type impurities. As shown in FIG. Characteristic method for manufacturing thin film transistors.