JPH01180657A - Control system for timer circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a timing circuit that measures the time until a response signal is transmitted after data is transmitted between a higher-level device and a lower-level device. The purpose of this system is to measure the time from when a higher-level device sends data to a lower-level device until a response signal is sent from the lower-level device to the higher-level device, and when the measured time is exceeded, This system has a clock circuit that sends a time-up signal to a lower-level device, and includes a clock time control section that sets the clock time of the clock circuit according to the type of control signal sent by the higher-level device. It is characterized by changing the clock time of the clock circuit depending on the content.

[Industrial application field]

The present invention relates to a timing circuit that measures the time until a response signal is transmitted after data is transmitted between a host device and a lower device.

Here, a system for applying the present invention will be explained based on the time charts of FIGS. 4 and 5.

-i's data transmission system first sends a call signal (address out) from the CPU 1 to the terminal device 2, and in the terminal device 2, for example, an operator or the like responds to the read signal from the keyboard (operational in). If it can be handled, a signal (address in) is sent to that effect. Thereafter, the CPU 1 sends a signal (command out) to the terminal device 2 connected via the controller 21 to the effect that data is about to be sent. If the terminal device 2 receives this signal and is ready to receive data, it cuts off the command out signal and returns a signal to that effect (status in) to the CPU 1. This establishes the data transmission/reception network (status) between the CPU 1 and the terminal device 2, but after this, the CPU 1 again sends a service out signal to the terminal device 2, and this signal is Data is transmitted to the terminal device 2 within a predetermined fixed time (this time can be arbitrarily set in a timer) taking skew into account. When the terminal device 2 side finishes receiving the data, it sends a signal to that effect (service in) to the CPU 1.

By doing this, data transmission and reception between the CPU 1 and the terminal device 2 is completed. CPU 1 is further connected to terminal device 2
If there is data to be sent to the terminal device 2, the service out signal is sent to the terminal device 2 again.

Note that the controller 21 uses a timer 40 to determine the above-mentioned predetermined period of time (time that varies depending on the amount of data).
It monitors whether data is being transmitted and received within the system, and it also monitors whether a plurality of types of control signals are being transmitted and received normally.

[Conventional technology]

Conventionally, the control method for a time measurement circuit (hereinafter referred to as a timer) is to control the CP by at least the number of control signals in advance, as shown in Fig. 6.
Channels 1a-1 to 1a-n are provided in U1. (In other words, the number of control signals and the number of channels have a one-to-one relationship) CP
The UI sends and receives control signals CO to and from the terminal device 2, and communicates desired data to the controller 2 using the data line DTL.
Normally, the control signal CO is sent and received to the terminal device 2 via the controller 21, and at the same time, a timer is used to monitor the time of the response signal sent from the terminal device 2 to the CPU 1. It is also sent to 3-1 to 3-n. Here, the arrival time of the control signal sent back from the terminal device 2 to the CPU 1 is monitored to see if a response is notified within the time set by the timer. When the control signal is not received from the terminal device 2, the timer 3-1 sends a time-up signal TU to the terminal device 2.

[Problem that the invention seeks to solve]

However, in the conventional timer control method, one timer measures one value, so if the number of values measured by the timer increases, the number of timers must increase accordingly, which requires less space for installing the timer. There were problems in that the size and cost were high.

Therefore, it is an object of the present invention to solve these problems and to enable a single clock circuit to measure multiple times.

[Means for solving problems]

Therefore, as shown in FIG.
The above object can be achieved by setting the clock time of the clock circuit 3 according to the type of control signal CO sent by the host device 1.

[Operation] With the above configuration, in the present invention, different clock times are set in advance in the clock time control section 4 in association with a plurality of types of control signals CO sent from the host device l. By changing the clocking time each time the control signal CO is sent to the clocking time control section 4,
It becomes possible to measure a plurality of values with one clock circuit 3.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail using FIGS. 2 and 3.

FIG. 2 shows one embodiment of the present invention, and FIG. 3 is a configuration diagram of a timer to which the present invention is applied.

First, the CPU 1 sends out a control signal CO via channels l a -A -n, and the sent control signal CO is divided into three branches, the first one is sent to the terminal device 2 via the controller 21, and the second one is sent to the terminal device 2 via the controller 21. is notified to the timer 3° via the OR circuit 25 and the delay timer 24, and the third is notified to the timer 3'' via the latch circuit 26. To explain specifically, the first
In the control signal CO notification, a control signal such as a call is sent to and received from the terminal device 2, and in the second control signal CO notification, the control signal is sent to and received from the timer 3 (specifically, the NOMOStable multivibrator 30 shown in FIG. 3). Apply the trigger and press the third
The control signal CO notification is used to decode a preset time constant according to the type of control signal CO (logically, the latch circuit 26 is not required here, but it is connected in the circuit for time adjustment). ). This decoder 23 determines in advance which MOS switch will be selected when which control signal CO is notified at the initial stage.

For example, to explain according to the previous example, in the case of address out, MOS switch 22-1 is selected,
What about status in? The OS switch 22-2 is selected. The timer 3' in the present invention includes a monostable multi-by-break 30, MOS switches 22-1 to 22-n for setting the time constant, and a resistor R1.
Since it is composed of "" n+ and a capacitor C, various clock times can be adjusted by freely selecting this CR (especially resistance value). Then, as in the past, a response signal is sent from the terminal device 2 to the CPU within the set time.
If the call is not received for terminal device 1, timer 3' (directly from monostable multipipulator 30) sends a call to terminal device 2.
A time-up signal TO is sent to the Incidentally, if a response signal is received from the terminal device 2 to the CPU 1 within the set time, the timer 3'' (more specifically, the monostable multi-bye break 30) is reset.

Note that when the time-up signal TO is notified to the terminal device 2, the controller 21 starts the timer 3 after a certain period of time.
A reset signal is notified to the monostable multi-high break 30 (specifically, the monostable multi-high break 30 shown in FIG. 3), and the time-up signal TO is reset.

Furthermore? The power supply V is constantly supplied to the OS switch 22-1-n.

〔Effect of the invention〕

As explained above, the present invention makes it possible to time multiple values with one timekeeping circuit, thereby eliminating the need for multiple timekeeping circuits, reducing the installation space for the timekeeping circuit, and reducing costs. becomes.

[Brief explanation of the drawing]

Fig. 1 shows a principle diagram of the present invention, Fig. 2 shows an embodiment of the invention, Fig. 3 shows a configuration diagram of a timer, and Fig. 4 shows a system diagram for applying the present invention. 5 shows a time chart for explaining the operation in FIG. 4, and FIG. 6 shows a conventional block diagram. In the figure, 1----------1st-level unit (CPU) + 1
a-1~n -----------・-channel, 2-・-
...-lower device (terminal device), 3--------
----Clock circuit (timer) + 4-・-・-Time constant control section. 21-1------ Controller, 23---
-------・-Decoder, 24--・--・-Delay timer, 25----------OR circuit, 26
...-1 latch circuit, 30・-----1--・-NOMO staple multi-by-break, CO-・--・--
--- Control signal, TU --- Indicates time-up signal, respectively. Timer screen diagram Figure 3

Claims (1)

[Claims] After the higher-level device (1) transmits data to the lower-level device (2), until the response signal is sent from the lower-level device (2) to the higher-level device (1). The time is measured, and when the measured time is exceeded, a time-up signal TU is sent to the lower device (2).
A system comprising a clock circuit (3) that transmits a signal to a clock, the system comprising: a clock time control system that sets the clock time of the clock circuit (3) according to the type of control signal CO sent by the host device (1); A control method for a timekeeping circuit, characterized in that a part (4) is provided, and the time measured by the timekeeping circuit (3) is changed according to the content of the control signal CO.