JPH01181221A - chopper type comparator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a CMOStII! used in a successive approximation type A/D converter, etc. Concerning a chopper type comparator.

(Prior art) In a chopper type comparator, a capacitor is connected to the input side of a linear amplifier, and a pair of input terminals for inputting signals to be compared are connected to this capacitor via a switch, respectively, and the input side and output side of the linear amplifier are connected to each other via a switch. An analog switch is connected between them, and the input signals are compared by on/off operations of the input signal switch and the analog switch of the linear amplifier.

FIG. 3 shows a conventional chopper type comparator.

I is an inverter for comparison as a linear amplifier, and P
It has an 0MO8 configuration consisting of MOS transistors and NMOS transistors, and has a high voltage power supply Vcc (5V) and G
Connected between ND and ND. One electrode of a capacitor C is connected to the input side of the inverter ■, a first input terminal is connected to the other electrode of the capacitor C via a switch S1, and a second input terminal is connected via a switch S2. It is connected.

The output side of the inverter I is connected to the output terminal, and PMOS transistors P and N are connected between the input side and the output side.
An analog switch consisting of a Mo5 transistor N is provided. A clock signal CK is input to the gate electrode of the PMOS transistor P, and a clock signal CK is input to the gate electrode of the NMo5 transistor N.
is inverted and input.

This chopper type comparator is connected to switch Sl.

The input signals A and B input to the input terminals are compared by controlling S2 and the analog switch to be turned on and off as shown in FIG.

The operation of the chopper type comparator shown in FIG. 3 will be explained using the operation curve diagram shown in FIG.

A pair of input signals Δ and B to be compared are given to inputs 1 and 2.

First, switch S1 and analog switch (CK) are turned on, and switch S2 is turned off. As a result, the input side and output side of inverter I are short-circuited, and both the input side voltage and the output side voltage are at the threshold voltage (0 on the operating curve in Figure 5).
point). When the threshold voltage is a, the input voltage A causes the capacitor C to store a charge of Q=C(A-a). C is the capacitance of capacitor C.

Next, the switch S1 is set to turn off the analog switch (CK), and the switch S2 is turned on. At this time, the input side voltage Vin of the inverter I from the charge storage side is (B - A
+a) is generated, and when (B-A)>0, the input side voltage Vin moves from O to 02 on the operating curve of Fig. 5, and the output of the comparator, that is, Vout, generates a voltage of b2, and the output becomes low level.

Conversely, when (B-A)<0, the input side voltage Vin is
Moving from O to Ol on the operating curve in the figure, the output of the comparator generates a voltage bl, and the output becomes high level.

In this way, due to the potential difference between input voltages A and H, input voltage A
Compare the size relationship between and B.

However, as shown in FIG. 3, the timing of the clock signal CK input to the gate electrode of the PMOS transistor P of the analog switch and the timing of the clock signal GK input to the gate electrode of the NMOS transistor N are different from each other. 4 is intervening, so it shifts.

As shown in FIG. 6, at the timing when the analog switch switches from on to off, the PMOS transistor P closes from time 1+ to the NMOS transistor N.
During the time Δt until closing time t2, the charge of the PMOS transistor P is dispersed through the NMO3 transistor N, and when the NMOS transistor N closes, the charge of the PMOS transistor P is distributed through the NMO3 transistor N.
Since the charge of the S transistor N is not dispersed,
The input potential of inverter (2) deviates from 0 in FIG. 5, resulting in an offset of the input signal of inverter (2).

(Objective) An object of the present invention is to prevent an offset of an input signal of a comparison linear amplifier caused by a phase difference between clock signals of analog switches of a CMOS chopper type comparator.

(Configuration) In the present invention, a capacitor is connected to the input side of a linear amplifier having a 0MO3 configuration, a pair of input terminals for inputting signals to be compared are connected to the capacitor through switches, and the input side of the linear amplifier is In the chopper type comparator, an analog switch is connected between the input signal switch and the output side, and the input signal is compared by the on/off operation of the analog switch and the input signal switch. The PMOS transistor and the MOS transistor, which are switched to OFF, are turned off at the same time, thereby preventing the occurrence of offset.

That is, in the present invention, the analog switch has two PM
Equipped with an OS transistor and two NMo5 transistors,
A clock signal is directly input to the gate electrode of one PMOS transistor, a clock signal is input to the gate electrode of the other PMOS transistor via a two-stage inverter, and a clock signal is input to the gate electrode of each NMOS transistor. was input through one stage of inverter, and the transistor size of the clock signal inverter was adjusted so that the timing of turning off the PMOS transistor and the NMOS transistor, which are turned off at the end, was the same.

Examples will be specifically described below.

FIG. 1 represents one embodiment.

As in Fig. 3, the reference inverter is used as a linear amplifier, has a 0MO5 configuration, and has a high voltage power supply Vcc.
(5V) and GND. Inverter ■
One electrode of a capacitor C is connected to the input side of the capacitor C, a first input terminal is connected to the other electrode of the capacitor C via a switch s1, and a second input terminal is connected to a switch s2.
connected via.

Two PMOS transistors PL and P are used as an analog switch to connect the input side and output side of the inverter ■.
2 and two NMo5 transistors Nl and N2 are used. Each MOS transistor P1, P2 . One electrode of Nl and N2 is connected to the input side of the inverter I, and the other electrode is connected to the output side.

The clock signal CK that operates the analog switch is P
It is directly input to the gate mt+ of the MOS transistor PL, is input to the gate electrode of the NMOS transistor N1 via the inverter Il, and is input to the gate mt+ of the NMOS transistor N2.
is input to the gate electrode of P via inverter ■2.
An inverter is connected to the gate electrode of MOS transistor P2.
2 and inverter 3.

Inverter Il, ■2. The size of the transistors constituting I3 is adjusted, and the inverter E1
The timing at which the output signal of the inverter 2 switches
and the timing at which the signal passing through 13 is switched are adjusted so that they are the same.

Next, the operation of this embodiment will be explained.

The operation of the comparator as a whole for comparing the signals of inputs 1 and 2 is explained in the fourth part of the explanation of the conventional comparator.
This is the same as explained using FIG.

Each MOS transistor Pl in the analog switch,
P2. The timing of the operations of Nl and N2 is different from the conventional one.

As shown in FIG. 2, at the timing of the clock signal CK, the PMOS transistor P! works, late NMO
S transistor N2 operates. Further delayed PMOS
Transistor P2 and NMOS transistor N1 operate simultaneously.

Thus, at the end of the on-to-off transition of the analog switch, the PMOS transistor P2
and NMOS transistor N1 are turned off at the same time, so
Both the charge of the PMOS transistor P2 and the charge of the NMOS transistor N1 remain without being dispersed, and cancel each other out to reduce the offset voltage.

(Effects) In the present invention, when the analog switch connecting the input side and output side of the linear amplifier is switched from on to off, the PMOS transistor and NMO3)-transistor that are switched last are turned off at the same time, so the offset voltage is reduced. decreases and improves the accuracy of the comparator.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment, Fig. 2 is a timing diagram showing the operation of an analog switch in the same embodiment, and Fig. 3 is a timing diagram showing the operation of an analog switch in the same embodiment.
The figure is a circuit diagram showing a conventional chopper type comparator.
5 is a diagram showing the operation timing of each switch of a chopper type comparator, FIG. 5 is a diagram showing an operation curve of the chopper type comparator, and FIG. 6 is a diagram showing the operation timing of analog switches in a conventional comparator. ■・・・・・・Inverter for comparison. ■1 to I3...Inverter. Pi, P2...PMOS transistor. Nl, N2...NMo5 transistor. C...Capacitor. SL, S2...Switch.

Claims (1)

[Claims] (1) A capacitor is connected to the input side of a CMOS-configured linear amplifier, and a pair of input terminals for inputting signals to be compared are connected to this capacitor through switches, respectively, and the input side and output side of the linear amplifier are connected to each other via a switch. In the chopper type comparator, an analog switch is connected between the input signals and the input signal is compared by on/off operation of the analog switch and the input signal switch.
A clock signal is directly input to the gate electrode of one PMOS transistor, and a clock signal is directly input to the gate electrode of one PMOS transistor.
Two clock signals are applied to the gate electrode of the MOS transistor.
A clock signal is inputted to the gate electrode of each NMOS transistor through one stage of inverters, and the clock signal is inputted to the gate electrode of each NMOS transistor through one stage of inverter, so that the timing of turning off the PMOS transistor and the NMOS transistor, which are turned off at the end, is the same. , a chopper type comparator characterized by adjusting the transistor size of the clock signal inverter.