JPH01181561A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate forming of an oxygen-doped silicon single crystal layer with excellent property of a single crystal by a method wherein, after polycrystalline silicon containing oxygen is deposited on a silicon substrate, silicon ions are implanted so that the substrate surface and the polycrystalline silicon film is made to be amorphous, and then the substrate surface and the amorphous silicon film are subjected to a thermal treatment for single- crystallization. CONSTITUTION:The required part of the main surface of a first conductivity type silicon single crystal substrate 1 is doped with an impurity to form a second conductivity type region 2. Then a silicone film 3 doped with oxygen and a first conductivity type impurity is formed on the second conductivity type region 2 and a silicon film 4 doped with a first conductivity type impurity is built up. Then silicon ions (Si<+>) are implanted so as to reach the silicon substrate 1 surface and the silicon films 3 and 4 and the silicon substrate 1 surface are made to be amorphous 3a and 4a. Further, a thermal treatment is carried out to change the amorphous regions into single-crystallized regions 3 and 4 by solid phase epitaxial growth. With this constitution, an emitter-base hetero-junction with excellent property of a single crystal can be obtained easily.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application) The present invention relates to a method for manufacturing a semiconductor Hrlt, and in particular to a method for manufacturing a bipolar transistor made of silicon.

(Conventional technology) In order to dramatically increase the speed of silicon bipolar transistors, it is necessary to replace the conventionally used silicon emitter with a so-called wide-gap emitter heterojunction material, which has a wider band gap than silicon. Is required.

When making a wide gap emitter.

Fabrication is performed by adding oxygen to silicon (Cζ). For example, 1 normal CVD method, S using ffi
I POS (SSem1-1nsulatin p
However, the emitter formed from this n+ has poor crystallinity and high resistance, and OXS EF (
OX)'ger-Doped Si Epitaxia
However, the MBEffl device has the problem of low mass productivity, and the manufacturing method using MBE is currently not practical.Also, in previous reports, oxygen-doped silicon was used for the emitter resistor due to the process. Because
There is a problem in that the emitter resistance increases.

Ideally, a wide gap is needed near the emitter-paste junction interface, and the entire emitter does not need to be wide-gap.

(Problem to be solved by the invention) The present invention has been made in consideration of the above circumstances.

The purpose of this is to easily form an oxygen-doped silicon single crystal layer with excellent single crystallinity when forming a silicon heterojunction bipolar transistor, reduce emitter resistance slightly, and significantly improve device performance. It is an object of the present invention to provide five methods for manufacturing semiconductor devices that can be used to produce semiconductor devices.

[Structure of the invention]

(Means to solve !II@) As a result of intensive study, we have decided to use LP on a silicon substrate.
After depositing polycrystalline silicon containing 10% to 50'4 of oxygen using the CVD method, implanting silicon ions into the polycrystalline silicon film to make the silicon substrate surface and the polycrystalline silicon film amorphous, When heat-treated at 650° C. to 700° C., it was found that the amorphous silicon became single crystallized at any oxygen concentration within the above range.

On the other hand, the oxygen concentration contained in polycrystalline silicon Ill was increased or decreased during the deposition process. In other words, the oxygen concentration was set to a maximum of 50 t during deposition of 100 A, and after further 200 A was deposited, the supply of oxygen was stopped, and the polycrystalline silicon pattern was
When 0OA-deposited wheat was subjected to silicon ion implantation and heat treatment in the same manner as described above, it was found that the amorphous silicon was crystallized to the surface.

An outline of the present invention based on the above knowledge will be explained using FIG. 1.

That is, first, as shown in FIG.
/70 to form a second ring type subregion (2). 15)
is a silicon oxide film.

Here, the method for adding the impurity may be ion implantation, diffusion from a gas atmosphere containing impurities, or diffusion from a thin film rich in impurities.

Next, as shown in FIG. 1b), at least the second conductor V
An oxygen and first type impurity doped silicon film (3) is formed on the t-type region (2), and then a first type impurity doped silicon film 4) is deposited.

Next, silicon ions (Sl
") is injected so as to reach the surface of the silicon cage plate, and the silicon pattern 13), +4) and the silicon substrate surface are made amorphous (3a), (4a).

Furthermore, as shown in FIG. 1(d), heat treatment is performed to form the amorphous regions into hand-crystallized regions (3b) and (4b) by solid phase epitaxial growth.

(Function) If a silicon heterojunction bipolar transistor is manufactured by the above process, an emitter-paste heterojunction with excellent single crystallinity can be easily obtained.

Furthermore, since it is possible to lower the emitter resistance, it is possible to significantly improve device properties.

(Implementation row) Two implementation rows according to the present invention will be described in detail below with reference to the drawings. FIG. 2 is a sectional view of the manufacturing process.

First, as shown in FIG. 2 (1a), a silicon oxide film is deposited on the surface of an n-type silicon substrate 161 with a p-type silicon substrate (with a thickness of 500× in the region of 50×, and masked in the region of (7a) as shown in the figure). +8) Impurity ions such as B (boron) were introduced using i at a voltage of 20 kV and an implantation amount of 3 x 1()”cm.
- Driven with snow, p-type semiconductor region (external base) (9)
was formed.

Next, as shown in FIG. 2(b), a G resist mask (
8) was removed, and B ions were applied to the entire surface at a voltage of 15 kV and an implantation amount of I x 10" cm to form a hand conductor base (10).

Here, the implantation depth of boron ions is shown in Figure 1 (a).
It may be shallower than the boron implant depth in .

Furthermore, as shown in Figure 2 (cl), silicon oxidation @ 1η with a width of 1.5 μm was obtained by hydrofluoric acid treatment using a resist mask.
An opening (11) was formed.

Next, as shown in Figure 2(d), f(As (arsenic)) was
．． 0 x 10! Ocm-”, O (oxygen) 1.0
X 10 "cm-" added JJD polycrystalline silicon g
After depositing (12) at 100A by LPCVD method,
In addition, polycrystalline silicon "Kan" 3) doped with As to 1x10 cm-" was processed using the LPCVD method
deposited.

The immersion in silicon ions (Fig. 2(e)
St) Wottoi electric EE40kV, driving*i
The polycrystalline silicon patterns (12), (13) and 1 hole (
11) Making the surface of the silicon substrate (6) amorphous (14)
(14a) Let it happen.

After that, as shown in the second figure, one row will be heated to 1150℃.
, D-lamp heat treatment was performed for 15 seconds, and an amorphous polycrystalline silicon film on the opening (11) was formed as a monocrystalline silicon film (15) by solid phase epitaxial growth.

Here, the silicon layer (16) on the oxide film (71, (7a)
) became polycrystalline.

Furthermore, as shown in Figure 2, a single crystal silicon layer (
The silicon layer (16) was removed leaving 15). This single crystal silicon layer (15) becomes an emitter region. Furthermore, as shown in Figure 2 (color), a silicon oxide film (17) of 3000A was deposited by the CVD method, and then the openings (17) were etched by reactive ion etching using a resist mask.
B) After providing (19), electrode aluminum layers (20) and (21) were formed.

The DC amplification factor of the NPN transistor formed by the above process is 400, and the circulation amplification factor of the NPN transistor fabricated without adding 0 (oxygen) during the deposition of polycrystalline silicon (t2) is 80. is C
Great improvement compared to ζ.

Next, the oxygen 6f of the polycrystalline silicon layer (12) (200Δ)
keJL at 50A at a position of 100A from the silicon substrate surface.
For simplicity, NPN transistors were fabricated above and below in the same manner as the above process except that the amount inside the machine was reduced to 10%. It is clear from Rutherford backscattering measurements that the single crystallinity of the silicon layer monocrystallized by the above process is improved compared to the example @1 described above. In other words, this release #! In Al, the bill lending density is preferably set to 10 to 50.

In addition, in this case, due to the reduction of crystal defects, the current l! 1@rate h
F) i was improved to 600.

Note that the present invention is not limited to the illustrative method described above. For example, As (arsenic) was used as the impurity in the emitter region, and P (I) was used as the impurity in the collector region, but the effect can be obtained even if the impurity in each region is As or P. That is clear. In addition, as a heat treatment method for solid-phase epitaxial growth, we used lamp chromatography, which causes less diffusion of impurities, but a normal horizontal furnace may also be used, and the diffusion of foreign substances can be kept within the desired range regardless of the temperature and time. As long as conditions are possible, conditions that allow solid phase epitaxial growth and activation of impurities may be used.

In addition, this Komei can be modified and implemented without departing from its gist.

[@Results of invention]

As detailed above, 1 (According to the present invention, an oxygen-doped silicon single crystal layer with a band gap wider than that of St can be easily formed at the emitter paste interface & a silicon heterojunction bipolar layer with high hF'E). It became possible to form transistors.

[Brief explanation of the drawing]

The eleventh is a process cut-off Ij for explaining the outline of the method of the present invention.
RI diagram and FIG. 2 are process cross-sectional views for explaining an embodiment according to the present invention. 1... First conductivity type silicon substrate, 2nd conductivity, lil region, 3... First conductivity type impurity and oxygen addition 7
111 polycrystalline silicon, 4... first conductive pear polycrystalline silicon. 5...Silicon oxide film, 6...@1 conductivity type silicon substrate, 7e7a...Silicon oxide film, 8...Resist mask, 9...External base elii*, 1'o...
・Internal heath area, 11...Opening part, 12...@1
4i1C type impurity and tvi element doped polycrystalline silicon model,
13... First conductivity type impurity doped polycrystalline silicon model, 1
4... Amorphous first isoelectrically impurity-added polysilicon film, 14a... Amorphous @1 conductive IC type impurity and oxygen-added polycrystalline silicon film, 15... Solid phase epitaxially grown vlL crystalline silicon region, 16...
- Polycrystalline silicon region, 17... silicon oxide film, 18.19... opening portion, 20... emitter electrode, 21... base electrode. Agent Patent Attorney Nori Ken Ken Yudo Ko Yama Hikaru 1st Diagram Φ Oan-ichino -noO'1=

Claims (2)

[Claims] (1) A step of adding an impurity to a part of the main surface of a first conductivity type silicon substrate to form a second conductivity type region, and adding a thin layer of oxygen and a first conductivity type impurity onto at least the second conductivity type region. forming a silicon film; forming a first conductivity type silicon pattern on the silicon film doped with oxygen and a first conductivity type; 1. A method for manufacturing a semiconductor device, comprising the steps of: implanting the silicon oxide film and the first conductivity type silicon film into a single crystal by heat treatment. (2) The oxygen concentration of the silicon film doped with oxygen and first conductivity type impurities has a desired maximum value of 50% or less within the film, and is formed so as to decrease in both upward and downward directions. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the following steps.