JPH01183236A - Communication control system for multi-processor system - Google Patents

Communication control system for multi-processor system

Info

Publication number
JPH01183236A
JPH01183236A JP63006987A JP698788A JPH01183236A JP H01183236 A JPH01183236 A JP H01183236A JP 63006987 A JP63006987 A JP 63006987A JP 698788 A JP698788 A JP 698788A JP H01183236 A JPH01183236 A JP H01183236A
Authority
JP
Japan
Prior art keywords
address
control
package
text
controlled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63006987A
Other languages
Japanese (ja)
Inventor
Kaoru Yoshida
薫 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63006987A priority Critical patent/JPH01183236A/en
Publication of JPH01183236A publication Critical patent/JPH01183236A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To shorten a communication time and to speed up control by adding a common address to respective controlled packages so as to transmit a control text. CONSTITUTION:A control package 1 and plural controlled packages 21-2n, all of which have processors, are connected by a communication path 3. An address 11 is extracted from the control text CT transmitted from a control package 1 in a control text reception part 21, and the address is compared with an address which has been set in an address setting part 23 in an address comparison part 22. When they coincide, s reception part 21 transmits a control command 12 to a command analysis part 24. When a global address is added to then control text CT as the address 11, respective controlled packages 21-2n receive them, and same control is attained by the one-time communication. Thus, the communication necessary time can be shortened and the speed up of control is realized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、プロセッサを有する制御パッケージと、各々
がプロセッサを有する複数の被制御パッケージとからな
るマルチ−プロセッサシステムにおいて、制御パッケー
ジが送信する制御テキストを被制御パッケージが受信を
行なう際に適用される通信制御方式に関するものである
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a multi-processor system consisting of a control package having a processor and a plurality of controlled packages each having a processor. The present invention relates to a communication control method applied when a controlled package receives text.

〔従来の技術〕[Conventional technology]

かかるマルチプロセッサシステムにおいては、各被制御
パッケージ毎に各個別のアドレスを定め、これを指定し
て制御パッケージが制御テキストの送信を行なうものと
なっておシ、この操作を各被制御パッケージ毎に行ない
、制御パッケージが各被制御パッケージの制御を順次に
行なうものとなっている。
In such a multiprocessor system, each individual address is determined for each controlled package, and the control package sends the control text by specifying this address.This operation is performed for each controlled package. The control package sequentially controls each controlled package.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、制御パッケージが各被制御パッケージに対し同
一の制御を行なう場合、制御テキストの送信を各被制御
パッケージ毎に行なわねばならず、これに要する通信時
間が増大し、制御上に遅延が生ずる問題を招来している
However, if the control package performs the same control on each controlled package, the control text must be sent to each controlled package, which increases the communication time required and causes a delay in control. is inviting.

〔課題を解決するための手段〕[Means to solve the problem]

前述の問題を解決するため、本発明はつぎの手段によシ
構成するものとなっている。
In order to solve the above-mentioned problem, the present invention is constructed by the following means.

すなわち、上述のマルチプロセッサシステムにおいて、
各被制御パッケージに共通のアドレスを含む複数のアド
レスを設定したアドレス設定部と、到来した制御テキス
ト中のアドレスとアドレス設定部のアドレスとを比較し
、一致したアドレスを含む制御テキストの受信を行なわ
せるアドレス比較部とを各被制御パッケージに設けるも
のとしている。
That is, in the multiprocessor system described above,
The address setting section sets multiple addresses including a common address for each controlled package, compares the address in the incoming control text with the address of the address setting section, and receives the control text containing the matching address. Each controlled package is provided with an address comparator section for controlling the address comparison section.

〔作用〕[Effect]

したがって、各被制御パッケージに共通のアドレスを付
加して制御テキストの送信を制御パッケージが行なうこ
とによシ、これが各被制御パッケージにおいて同時に受
信されるものとなシ、同一の制御を1回の通信によシ行
なうことができる。
Therefore, by adding a common address to each controlled package and sending the control text, the control package receives the control text at the same time in each controlled package. This can be done through communication.

〔実施例〕〔Example〕

以下、実施例を示す図によって本発明の詳細な説明する
Hereinafter, the present invention will be explained in detail with reference to figures showing examples.

第2図は全構成を示すブロック図であり、各々がプロセ
ッサを有する制御パッケージ1および複数の被制御パッ
ケージ21〜2nが通信路3によシ接続されておシ、相
互間において通信路3を介するデータの送受信を行ない
、制御パッケージ1による制御にしたがい、各被制御パ
ッケージ2.〜2nが各々所定の制御処理を実行するも
のとなっている。
FIG. 2 is a block diagram showing the entire configuration, in which a control package 1 and a plurality of controlled packages 21 to 2n, each having a processor, are connected by a communication path 3. According to the control by the control package 1, each controlled package 2. .about.2n each execute a predetermined control process.

第3図は、制御パッケージ1が送信する制御テキストの
構成を示す図であシ、受信すべき被制御パッケージを指
定するアドレス11、および、制御コマンド12によ)
構成されておシ、被制御パッケージ21〜2nにおいて
は、匍制御テキスト中のアドレス11と自己のアドレス
とを比較し、一致したとき制御テキストを受信すべきも
のと判断し、制御コマンド12の解析を行なったうえ、
これの内容を笑行するものとなっている。
FIG. 3 is a diagram showing the structure of the control text sent by the control package 1, which includes an address 11 specifying the controlled package to be received and a control command 12).
The controlled packages 21 to 2n compare the address 11 in the control text with their own address, and when they match, determine that the control text should be received, and analyze the control command 12. In addition to doing so,
The content of this is meant to be funny.

第1図は、制御テキストの受信処理回路を示すブロック
図であシ、制御パッケージ1から送信された制御テキス
) CTは、制御テキスト受信部21においてアドレス
11が抽出され、アドレス比較部22へ与えられたうえ
、アドレス設定部23に設定されたアドレスとの比較が
行なわれ、一致した場合はアドレス比較部22がこの結
果を制御テキスト受信部21へ与えるため、同受信部2
1が制御コマンド12をコマンド解析部24へ送出する
ものとなシ、ここにおいて制御コマンド12の解析がな
され、これにより制御テキストCTの受信が行なわれる
FIG. 1 is a block diagram showing a control text reception processing circuit. In the control text CT (control text transmitted from the control package 1), an address 11 is extracted in the control text reception section 21 and is sent to the address comparison section 22. In addition, a comparison is made with the address set in the address setting section 23, and if they match, the address comparison section 22 gives this result to the control text reception section 21, so that the same reception section 2
1 sends the control command 12 to the command analysis section 24, the control command 12 is analyzed here, and the control text CT is thereby received.

ただし、アドレス設定部22には、各被制御パッケージ
21〜2nに共通のグローバルアドレス、および、各個
別のアドレス等、複数のアドレスがあらかじめ設定して
あシ、制御テキストCTヘゲローバルアドレスがアドレ
ス11として付加された場合は、各被制御パッケージ2
□〜2nのアドレス比較部22が同時Gで一致出力を生
ずるものとな  4シ、各被制御パッケージ21〜2n
が一斉に制御テキス) CTの受信を行なうため、制御
パッケージ1は1回の送信を行なうのみにより、同一の
制御を各被制御パッケージ21〜2111に対して同時
に行なうことができる。
However, in the address setting section 22, a plurality of addresses such as a global address common to each controlled package 21 to 2n and each individual address are set in advance, and the control text CT hegeglobal address is an address. 11, each controlled package 2
The address comparators 22 of □~2n are to produce matching outputs at the same time.4, each controlled package 21~2n
Since the control package 1 receives the CT (control text) all at once, the control package 1 can simultaneously perform the same control on each of the controlled packages 21 to 2111 by transmitting only one time.

〔発明の効果〕〔Effect of the invention〕

以上の説明によシ明らかなとおり本発明によれば、各被
制御パッケージに共通のアドレスを含む複数のアドレス
を設定したアドレス設定部と、到来した制御テキスト中
のアドレスとアドレス設定部のアドレスとを比較し、一
致したアドレスを含む制御テキストの受信を行なわせる
アドレス比較部とを設けることによシ、共通のグローバ
ルアドレスを付加して制御テキストを送信すれば、これ
が各被制御パッケージにおいて一斉に受信されるものと
なシ、同一の制御を1回の通信によシ行なえるため、通
信所要時間の短縮および制御の高速化が笑現し、各種用
途のマルチプロセッサシステムにおいて顕著な効果が得
られる。
As is clear from the above explanation, according to the present invention, there is provided an address setting section in which a plurality of addresses including a common address are set for each controlled package, and an address in an incoming control text and an address in the address setting section. By providing an address comparison section that compares the addresses and receives the control text containing the matched address, if the control text is sent with a common global address added, this can be done simultaneously in each controlled package. Since the same control can be performed in a single communication regardless of what is being received, communication time can be shortened and control speed can be increased, resulting in remarkable effects in multiprocessor systems for various purposes. .

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の実施例を示し、第1図は受信処理回路のブ
ロック図、第2図は全構成のブロック図、第3図は制御
テキストの構成を示す図である。 1・・・・制御パッケージ、21〜2n・・・・被制御
パッケージ、11・鳴・・アドレス、12・・・・制御
コマンド、22・・・・アドレス比較部、23・・・・
アドレス設定部、24・・・・コマンド解析部。
The figures show an embodiment of the present invention; FIG. 1 is a block diagram of a reception processing circuit, FIG. 2 is a block diagram of the entire configuration, and FIG. 3 is a diagram showing the configuration of control text. 1... Control package, 21-2n... Controlled package, 11... Address, 12... Control command, 22... Address comparison unit, 23...
Address setting section, 24... Command analysis section.

Claims (1)

【特許請求の範囲】[Claims] プロセッサを有する制御パッケージと、各々がプロセッ
サを有する複数の被制御パッケージとからなるマルチプ
ロセッサシステムにおいて、前記各被制御パッケージに
共通のアドレスを含む複数のアドレスを設定したアドレ
ス設定部と、到来した制御テキスト中のアドレスと前記
アドレス設定部のアドレスとを比較し一致したアドレス
を含む制御テキストの受信を行なわせるアドレス比較部
とを前記各被制御パッケージに設けたことを特徴とする
マルチプロセッサシステムの通信制御方式。
In a multiprocessor system consisting of a control package having a processor and a plurality of controlled packages each having a processor, an address setting section that sets a plurality of addresses including a common address to each of the controlled packages, and an incoming control Communication in a multiprocessor system, characterized in that each controlled package is provided with an address comparison section that compares an address in the text with an address in the address setting section and receives a control text containing a matched address. control method.
JP63006987A 1988-01-18 1988-01-18 Communication control system for multi-processor system Pending JPH01183236A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63006987A JPH01183236A (en) 1988-01-18 1988-01-18 Communication control system for multi-processor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63006987A JPH01183236A (en) 1988-01-18 1988-01-18 Communication control system for multi-processor system

Publications (1)

Publication Number Publication Date
JPH01183236A true JPH01183236A (en) 1989-07-21

Family

ID=11653506

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63006987A Pending JPH01183236A (en) 1988-01-18 1988-01-18 Communication control system for multi-processor system

Country Status (1)

Country Link
JP (1) JPH01183236A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013513733A (en) * 2009-12-11 2013-04-22 エーリコン テクスティル ゲゼルシャフト ミット ベシュレンクテル ハフツング ウント コンパニー コマンディートゲゼルシャフト Control device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60246151A (en) * 1984-05-21 1985-12-05 Canon Inc Data transmission system
JPS6199439A (en) * 1984-09-29 1986-05-17 Fujitsu Ltd Group address communication system
JPS6224741A (en) * 1985-07-25 1987-02-02 Matsushita Electric Works Ltd Multiplex transmission system
JPS62200838A (en) * 1986-02-28 1987-09-04 Toshiba Corp Multiple address message transmission/reception system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60246151A (en) * 1984-05-21 1985-12-05 Canon Inc Data transmission system
JPS6199439A (en) * 1984-09-29 1986-05-17 Fujitsu Ltd Group address communication system
JPS6224741A (en) * 1985-07-25 1987-02-02 Matsushita Electric Works Ltd Multiplex transmission system
JPS62200838A (en) * 1986-02-28 1987-09-04 Toshiba Corp Multiple address message transmission/reception system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013513733A (en) * 2009-12-11 2013-04-22 エーリコン テクスティル ゲゼルシャフト ミット ベシュレンクテル ハフツング ウント コンパニー コマンディートゲゼルシャフト Control device

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