JPH01185992A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH01185992A JPH01185992A JP1168288A JP1168288A JPH01185992A JP H01185992 A JPH01185992 A JP H01185992A JP 1168288 A JP1168288 A JP 1168288A JP 1168288 A JP1168288 A JP 1168288A JP H01185992 A JPH01185992 A JP H01185992A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- sided
- conductor layer
- hole
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〈産業上の利用分野さ
本発明は、両面印刷回路板の製造方法の改良に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an improvement in the method of manufacturing double-sided printed circuit boards.
〈従来の技術〉
印刷回路板において、スルホールを有する導体回路を形
成する場合、両面銅張り基板(または片面銅張り基材の
他面に銅箔を接着したもの)にスルホール用穴を設け、
基材全面に銅を無電解メッキし、その全面にメンキレジ
ストを被覆し、次いで、露光・現象によりスルホール部
を露出させ、このft出スルホール部に銅を電解メッキ
し、このメッキ後に、上記レジストを除去し、而るのち
、全面に新にエツチングレジストを被覆し、露光・現象
により所定パターン(導体回路パターンに対しネガ)で
銅面を露出さ廿、この露出銅面をエツチングして導体回
路を形成している。<Prior art> When forming a conductor circuit with through-holes in a printed circuit board, holes for through-holes are provided in a double-sided copper-clad substrate (or a single-sided copper-clad substrate with copper foil adhered to the other side).
Copper is electrolessly plated on the entire surface of the base material, the entire surface is coated with Menki resist, the through holes are exposed by exposure and phenomenon, copper is electrolytically plated on the ft through holes, and after this plating, the above resist is applied. After that, the entire surface is covered with a new etching resist, and the copper surface is exposed in a predetermined pattern (negative for the conductor circuit pattern) by exposure and phenomenon.Then, this exposed copper surface is etched to form the conductor circuit. is forming.
〈解決しようとする問題点〉
しかしながら、この方法では、スルホールメッキのラン
ド部に段差が発生し、上記エツチングレジスト被膜にも
段差が生じるので、このレジスト被膜とフォトマスクと
の密着性が悪くなり、上記所定パターン(導体回路パタ
ーンに対しネガ)で露光するときに顕著なハレーシラン
の発生が避けられず、導体回路の寸法精度の低下を免れ
得ない。<Problems to be Solved> However, in this method, a step occurs in the land portion of the through-hole plating, and a step also occurs in the etching resist film, which deteriorates the adhesion between the resist film and the photomask. When exposing with the above-mentioned predetermined pattern (negative for the conductor circuit pattern), the generation of noticeable haley silane is unavoidable, and the dimensional accuracy of the conductor circuit is inevitably reduced.
もっとも、導体回路パターンを形成してからランド部を
メッキすれば、かかる不利は回避できるから、この方法
では導体回路(非連続)をメッキのためのリード導体に
利用できないので、別途にメッキリードを設ける必要が
あり、ランドのメッキ作業が煩雑となる。However, this disadvantage can be avoided by plating the land portions after forming the conductor circuit pattern.With this method, the conductor circuit (discontinuous) cannot be used as a lead conductor for plating, so plated leads must be prepared separately. Therefore, the land plating work becomes complicated.
本発明の目的は、上記ハレーションを排除でき、しかも
、別途のメッキリードを必要としない印刷回路板の製造
方法を提供することにある。An object of the present invention is to provide a method for manufacturing a printed circuit board that can eliminate the above-mentioned halation and does not require a separate plating lead.
〈問題点を解決するための技術的手段〉本発明に係る印
刷回路板の製造方法は、絶縁支持体の片面に導体層Aを
設けた片面導体絶縁板の他面に上記導体層Aよりも薄い
導体層Bを設け、該両面導体絶縁体にスルホール用穴を
加工し、該穴並びに導体層B上に導体材をメッキして、
両面の導体層を化学エツチングに対し両等の厚みになし
、而るのち、両面導体層を所定のパターンに形成するこ
とを特徴とする方法である。<Technical Means for Solving the Problems> The method for manufacturing a printed circuit board according to the present invention includes a single-sided conductor insulating plate having a conductor layer A on one side of an insulating support, and a conductor layer A on the other side of the insulating support. A thin conductor layer B is provided, a hole for a through hole is formed in the double-sided conductor insulator, and a conductor material is plated on the hole and the conductor layer B.
This method is characterized in that the conductor layers on both sides are made to have the same thickness by chemical etching, and then the conductor layers on both sides are formed into a predetermined pattern.
〈実施例の説明〉 以下、図面により本発明を説明する。<Explanation of Examples> The present invention will be explained below with reference to the drawings.
第1図は両面導体絶縁板Pを示している。第1図におい
て、1は片面導体絶縁板であり、プラスチックフィルム
、シートまたはプレート11の片面に接着剤12により
圧延gA箔Aを積層しである。Bは絶縁板11の他面に
設けた導体層例えば接着剤22により積層した銅箔(圧
延w4箔または電解銅箔)であり、その厚みは、上記片
面の導体NAよりも小である。FIG. 1 shows a double-sided conductor insulating plate P. In FIG. 1, reference numeral 1 denotes a single-sided conductive insulating plate, in which a rolled gA foil A is laminated on one side of a plastic film, sheet or plate 11 with an adhesive 12. B is a conductor layer provided on the other side of the insulating plate 11, for example, a copper foil (rolled W4 foil or electrolytic copper foil) laminated with an adhesive 22, and its thickness is smaller than the conductor NA on one side.
本発明を実施するには、第2図に示すように、スルホー
ル用穴3を加工し、このスルホール用穴3並びに他面の
導体NBのみに導体材C(Ii)をメッキしく銅を化学
メッキし、そのうえに銅を電解メンキする)、他面の全
導体層(B C)の厚みを片面の導体iAの厚みに化学
エツチングに対して同等にする(エツチング液、エツチ
ング時間等のエツチング条件同一のもとで、各導体層の
全厚みをエツチングできるようにする)。この場合、善
導体層A並びに(B C)の各厚みは厳密には圧延銅、
化学メッキ銅、電解メッキ銅等の腐食性の相違により異
るが、通常はほぼ同厚とすればよく、例えば、片面の圧
延GIA箔Aが35μ閤の場合、他面の圧延または電解
銅箔Bを18μm、そのうえの銅メッキ層Cの厚みを1
8μmとすればよい。To carry out the present invention, as shown in FIG. 2, a through-hole hole 3 is processed, and only the through-hole hole 3 and the conductor NB on the other side are plated with conductor material C (Ii) and copper is chemically plated. Then, the thickness of the entire conductor layer (B to allow etching of the full thickness of each conductor layer). In this case, the thickness of each of the good conductor layers A and (B C) is strictly speaking rolled copper,
Although it differs depending on the corrosivity of chemically plated copper, electrolytically plated copper, etc., it is usually sufficient to have approximately the same thickness. For example, if the rolled GIA foil A on one side has a thickness of 35μ, the rolled or electrolyzed copper foil on the other side. B is 18 μm, and the copper plating layer C on top is 18 μm thick.
It may be 8 μm.
上記、スルホール用穴並びに片面導体層に導体材をメ7
・キするには、第3図に示すように、両面導体絶縁板P
、 (P)を片面において絶縁板1を介して重畳し、
スルホール用穴3を設け、各両面導体絶縁板P、 C
P)のスルホール内入3.+31並びに他面導体層B、
(B)導体材Cを一挙にメッキすればよい。Above, attach conductive material to the through-hole hole and single-sided conductor layer.
・To do this, use a double-sided conductor insulating plate P as shown in Figure 3.
, (P) are superimposed on one side through the insulating plate 1,
Hole 3 for through hole is provided, and each double-sided conductor insulation plate P, C
P) through-hole insertion 3. +31 and the other side conductor layer B,
(B) The conductor material C may be plated all at once.
而るのちは、各面導体層上にエツチングレジストを被覆
し、各レジスト膜上にフォトマスクを密着させ、露光を
行い、更に、現象して、各面導体層を導体回路パターン
に対してネガのパターンで露出させ、次いで導体をエツ
チングして所定の導体回路パターンを形成する。Afterwards, each surface conductor layer is coated with an etching resist, a photomask is closely attached to each resist film, and exposure is performed. The conductor is then etched to form a predetermined conductor circuit pattern.
上記導体層Bは、スルホール穴3の周辺においても平坦
であり、フォトマスクを導体層Bの全面に密着させ得る
から、ハレーションを情無にして露光できる。また、善
導体層A並びに(BC)の厚みを化学エツチングに対し
て同等にしであるから、両導体を同一のエツチング条件
でエツチングできる。The conductor layer B is flat even around the through holes 3, and the photomask can be brought into close contact with the entire surface of the conductor layer B, so that exposure can be performed without causing halation. Furthermore, since the thicknesses of the good conductor layers A and (BC) are made the same for chemical etching, both conductors can be etched under the same etching conditions.
第4図A、乃至第4図りは、両端部には両面に印刷導体
を設け、中央部には、片面のみに印刷導体を設けたフレ
キシブルプリント回路(第4図E)の製造方法に対する
実施例を示している。Figure 4A to Figure 4 are examples of the method for manufacturing a flexible printed circuit (Figure 4E) in which printed conductors are provided on both sides at both ends and printed conductors are provided only on one side in the center. It shows.
゛片面導体絶縁板1には、プラスチックフィルム(例え
ば、厚さ25〜75μ愼のポリイミドフィルム)11の
片面に接着剤(例えば、厚さ10〜30μ喝のエポキシ
系接着剤)12により圧延銅Fg(厚さ35μR1)A
を積層したものを用いる。゛For the single-sided conductor insulating board 1, rolled copper Fg is attached to one side of a plastic film (for example, a polyimide film with a thickness of 25 to 75 μm) 11 with an adhesive (for example, an epoxy adhesive with a thickness of 10 to 30 μm) 12. (thickness 35μR1) A
A laminated layer is used.
この片面導体絶縁板1の他面に、第4図A並びに第4図
Bに示すように、中間部を打抜いた枠状接着剤22を介
して薄肉銅箔(厚さ18μmの圧延銅箔)Bをベースラ
ミネーションプレス又はロールラミネーシヲンで接着す
る(150 ”〜170 ’C,10kg/d 〜40
kg/c+J、30〜60分の条件)。As shown in FIGS. 4A and 4B, a thin copper foil (18 μm thick rolled copper foil ) Adhere B using base lamination press or roll lamination (150''~170'C, 10kg/d~40
kg/c+J, 30-60 minutes).
次いで、前記と同様にして、第4図Cに示すように、ス
ルホール用穴3,3を加工し、このスルホール用穴3と
薄肉銅箔B上に銅Cをメンキし、両面の導体A並びに(
BC)が化学エツチングに対して同等となるように、そ
の銅メッキ厚さを所定厚み(18μm)にする。Next, in the same manner as described above, as shown in FIG. (
The copper plating thickness is set to a predetermined thickness (18 μm) so that BC) is equivalent to chemical etching.
而るのちは、両面にエツチング、レジストを被覆し、所
定の各フォトマスクを各導体面に密着し、露光・現象に
より、第4図りに示すように、導体回路パターンのパタ
ーンにてレジストlia並びに(b c)を残存させ、
各面の露出銅箔部分をエツチングし、第4図Eに示す製
品を得る。After that, both sides are coated with etching and resist, each predetermined photomask is closely attached to each conductor surface, and by exposure and phenomenon, the resist lia and resist are formed in the pattern of the conductor circuit pattern as shown in Figure 4. (b c) remains;
The exposed copper foil portions on each side are etched to obtain the product shown in FIG. 4E.
〈発明の効果〉
本発明に係る印刷回路板の製造方法は、上述した通りの
方法であり、スルホール用穴内面をメッキすると同時に
他面の導体層全面をメンキしており、その全面平坦なメ
ッキ導体面にレジストを被覆し、この平坦面をフォトマ
スクによって露光できるから、ハレーションを回避でき
る。勿論、導体層をメッキリードに利用できるから、メ
ッキも容易である。また、両面の導体層を化学エツチン
グに対して同等の厚さとしているから、両面を同一条件
でエツチングでき、従来と同様にして両面導体回路の形
成が可能である。<Effects of the Invention> The method for manufacturing a printed circuit board according to the present invention is the method described above, in which the inner surface of the through-hole hole is plated and the entire surface of the conductor layer on the other surface is peeled at the same time, and the entire surface is flatly plated. Halation can be avoided because the conductor surface is coated with resist and this flat surface can be exposed using a photomask. Of course, since the conductor layer can be used as a plating lead, plating is also easy. Further, since the conductor layers on both sides are made to have the same thickness for chemical etching, both sides can be etched under the same conditions, and a double-sided conductor circuit can be formed in the same manner as in the conventional method.
第1図乃至第3図は本発明の一実施例を示す説明図であ
り、第1図は両面導体絶縁板を、第2図は導体材のメッ
キ後を、第3図は導体中のメッキ時をそれぞれ示してい
る。第4図A、第4図B1第4図C1第4図り並びに第
4図Eは本発明における別実流側の両面導体絶縁板、同
絶縁板の枠状接着剤、メッキ後の状態、エツチング直前
の状態並びに印刷回路板をそれぞれ示している。
図において、11は絶縁支持体、Aは導体層、Bは薄い
導体層、1は両面導体絶縁板、3はスルホール用穴、C
はメッキ導体材である。Figures 1 to 3 are explanatory diagrams showing one embodiment of the present invention. Figure 1 shows a double-sided conductor insulating plate, Figure 2 shows the conductor material after plating, and Figure 3 shows the plating in the conductor. Each shows the time. Figure 4A, Figure 4B1, Figure 4C1, Figure 4C, and Figure 4E show the double-sided conductor insulating plate on the separate flow side in the present invention, the frame adhesive of the same insulating plate, the state after plating, and the etching. The previous state as well as the printed circuit board are respectively shown. In the figure, 11 is an insulating support, A is a conductor layer, B is a thin conductor layer, 1 is a double-sided conductor insulating plate, 3 is a hole for a through hole, C
is a plated conductor material.
Claims (1)
の他面に、上記導体層Aよりも薄い導体層Bを設け、該
両面導体絶縁板にスルホール用穴を加工し、該穴並びに
導体層B上に導体材をメッキして、両面の導体層を化学
エッチングに対し、同等の厚みになし、而るのち、両面
導体層を所定の導体パターンに形成することを特徴とす
る印刷回路板の製造方法。A conductor layer A is provided on one side of the insulating support, and a conductor layer B thinner than the conductor layer A is provided on the other side of the insulating support, a through hole is formed in the double-sided conductor insulator, and the holes and A printed circuit characterized in that a conductor material is plated on the conductor layer B, the conductor layers on both sides are made to have the same thickness against chemical etching, and then the double-sided conductor layers are formed into a predetermined conductor pattern. Method of manufacturing the board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1168288A JP2530678B2 (en) | 1988-01-20 | 1988-01-20 | Method of manufacturing printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1168288A JP2530678B2 (en) | 1988-01-20 | 1988-01-20 | Method of manufacturing printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01185992A true JPH01185992A (en) | 1989-07-25 |
| JP2530678B2 JP2530678B2 (en) | 1996-09-04 |
Family
ID=11784777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1168288A Expired - Lifetime JP2530678B2 (en) | 1988-01-20 | 1988-01-20 | Method of manufacturing printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2530678B2 (en) |
-
1988
- 1988-01-20 JP JP1168288A patent/JP2530678B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2530678B2 (en) | 1996-09-04 |
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