JPS606143B2 - Input data state change detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input data state change detection circuit that detects a change in the state of data by checking when various data sent from a telemeter or the like changes during normal operation.

Conventionally, data sent from a telemeter has been subject to instantaneous changes, such as interruptions, due to the influence of transmission noise and the like, and these have sometimes been detected as data.

As a countermeasure to this problem, an integration circuit composed of resistors, capacitors, etc. is used to absorb the noise, but there is also a problem in the way the time constant is determined, making it difficult to reliably detect changes in the data state. The above will be explained with reference to the block diagram in FIG. 1 and the time chart in FIG. 2. In the figure, 1 is an input terminal to which input data is input, 2 is a holding memory circuit, 3 is a terminal to which a sampling pulse is input, and 4 is an output terminal.

FIG. 2 shows a data timing chart for explaining FIG. 1. In the figure, 5 indicates a sampling pulse, 6 indicates input data, and 7 indicates a holding memory output.

In FIG. 1, input data 6 input to input Satoko 1
is input to the holding memory 2, and an output 7 is output from the holding memory 2 by the sampling pulse 3. In this case, the ■ part of the input data is sustained data with 1 level, and the ■ part is data that has momentary interruptions due to the influence of noise on the transmission path, so in reality, the 1 level of ■ is sustained. It is something. Nevertheless, the output of the retained memory is
′ is output. Since this data 7 contains errors, if it is output as data, it will cause a problem in the telemeter system. In order to solve the above-mentioned problems, the present invention provides an input data state change detection circuit that detects only normal data, excluding data at the time of a break. For this purpose, it is established that {1' the pulse width t of data adjacent to each other due to the above-mentioned transmission line noise etc. is set to be T>t with respect to the sampling pulse T, and ① the interval of continuous data>phantom. [1], Under the conditions of [21], data input to an n-bit shift register is shifted using a sampling pulse, and the output of the shift register is changed to a state composed of an exclusive OR circuit, an inverter, and an AND circuit. By detecting changes in the state of data with a detection circuit, changes in the state of input data can be confirmed and the information system can operate stably. This will be explained below with reference to the embodiment shown in FIG. 3 and the time chart shown in FIG. 4.

In this embodiment, a shift register having a 3-bit configuration will be explained. In FIG. 3, 1 and 3 are the same members as in FIG. 1, 10 is a shift register, 11 is the first bit of the shift register 10, 12 is the second bit of the shift register 10, 13 is the third bit of the shift register, 14 is a state change detection circuit, 15 and 16 are exclusive OR circuits (hereinafter referred to as EXO
17 is an inverter, 18 is an AND circuit,
Reference numeral 19 indicates a state change detection signal output terminal, 20 indicates a control pulse output circuit, 21 indicates a holding memory circuit, and 22 indicates an output terminal of the holding memory circuit.

In FIG. 4, 25 is a sampling pulse, 26 is input data, 27 is a state change detection signal, 28 is a control pulse, 2
9 indicates the holding memory output, and 30 indicates the delay time Δt.

Next, in FIGS. 3 and 4, when the input data 26 input from the input terminal 1 is shifted at the periods T, , T2, and T3 of the sampling pulse 25 input to the shift register 0, the first bit 11 and the The second bit is shifted to 12, and the third bit is shifted to 13. Now, the data of the first bit 11, the second bit 12, and the third bit 13 are 0, 1, 1. Data of 0 and 1 is input to EXOR 15, and the output becomes 1. Data of 1 and 1 is input to EXOR 16, and the output is inverted by inverter 17 to become 1. Then, 1 and 1 are input to the AND circuit 18, and as a result, the condition change detection signal 27 is detected. As described above, in the state change detection circuit 14, the first bit, the second bit, and the third bit of the shift register 10 are
When the combination of bits is 0, 1 "1" or 1, 0, 0, the state change detection signal 27 is output.The state change detection signal and the sampling pulse are input to the control pulse output circuit 20, from which the sampling pulse Δt A delayed control pulse 28 is output, and this control pulse 28 causes the third bit, 13, to be stored in the holding memory circuit, and the holding memory is outputted from the output terminal 3.Next, the input data 26 is affected by noises such as ■. The state change detection signal and the state of the holding memory circuit 21 when the state change detection signal has a pulse (pulse width t) will be explained. The combination of bits must be 0, 1, 1 or 1, 0, 0, so in this case the bit combination is 0 in Figure 4-26.
The data of , 1, 1 becomes the points of ■, ◎, and ■. Also the third
The bit is at one level, and this one level is held by the memory circuit 21.
When inputted into , the continuous data at point g in the holding memory 29 is output, and the Fujicut ■ in the input data 26 can be removed. The above is a description of one embodiment. In the operation of the present invention, erroneous input data due to instantaneous interruptions can be removed by appropriately varying the sampling pulse interval. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a subordinate example, FIG. 2 is a time chart for explaining FIG. 1, FIG. 3 is an embodiment of the present invention, and FIG. 4 is for explaining FIG. 3. The following is a time chart for this.

10 is a shift register, 14 is a state change detection circuit, 15, 1
6 is an exclusive OR circuit, 17 is an inverter, and 18 is an AN
D circuit, 20 is a control pulse output circuit, and 21 is a holding memory circuit. Figure 1 Figure 2 Figure 3 Hair Figure 4

Claims (1)

[Claims] 1 An n-bit shift register that shifts input data according to a timing clock, and 2 bits of the shift register.
An exclusive OR circuit that inputs the contents of bits into pairs and shares them with adjacent bits, and a first exclusive OR circuit that inputs the contents of the two bits furthest from the input end of the shift register. an inverter circuit connected to each output stage of an exclusive OR circuit other than the first exclusive OR circuit, an AND circuit to which the outputs of the first exclusive OR circuit and the inverter circuit are input, and an output of the AND circuit and a timing clock. 1. An input data state change detection circuit comprising a holding circuit that holds the contents of the bit closest to the input of the shift register according to the input data.