JPH0531973B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] When synchronizing the frame of data including error correction codes, the error detection signal generated in the error correction circuit is used as frame synchronization information indicating whether or not synchronization is achieved. This enables high-speed frame synchronization without reducing frame bits, that is, the amount of information that can be transmitted.

[Industrial application field]

The present invention relates to an improvement in a high-speed frame synchronization method for data including information added with an error correction code.

For example, in the case of audio coding transmission in which feature parameters of audio are extracted and transmitted as auxiliary information together with other information, an error correction code is added to the auxiliary information. This auxiliary information is provided on a block-by-block basis.

In such a case, as shown in FIG. 4, the frame bit F and the block code section A are at a constant time interval indicated by a, and synchronization is established using the frame bit F. Furthermore, the block code portion A is detected based on the position of the frame bit F, and the error correction circuit outputs an error detection signal. In this case, once frame synchronization is achieved, almost no error detection signal is generated unless an error occurs due to a failure in the transmission path or the like.

[Conventional technology]

A conventional high-speed frame synchronization method will be described below with reference to the drawings.

FIG. 3 is a block diagram of the main parts of a conventional receiving section.

In FIG. 3, input data including an error correction block code is input to a comparison circuit 4' and an error correction circuit 2 of a frame synchronization circuit 1'.

The comparison circuit 4' compares the input data with the frame signal from the frame counter 6', and if they do not match, a mismatch signal is input to the frame protection circuit 5', and when the mismatch signal occurs n times, a 1-bit shift is performed. By outputting the pulse to the AND circuit 7 with inversion and inhibiting the receiving bit clock by 1 bit, it is possible to synchronize the output of the frame counter 6' by 1 bit and sending the frame signal shifted by 1 bit to the comparator circuit 4'. Repeat until
Perform synchronous pull-in.

On the other hand, the error correction circuit 2 includes a frame counter 6'.
The logical AND output of the frame bit signal and shift pulse from the block code section A is found based on this output, error correction is performed, and the error-corrected data is output as received data.

In this case, for example, if a frame signal is composed of one frame bit per frame and four bits for four frames, pseudo synchronization often occurs because the number of frame bits is small.

Therefore, it is necessary to lengthen the backward protection time in the frame protection circuit 5', which is a period for identifying the completion of true synchronization pull-in, and it takes time to pull-in the synchronization.

Therefore, for example, if the frame bits per frame are set to 2 bits and the frame signal is made up of 8 bits for 4 frames, false synchronization will be less likely to occur, and the backward protection time in the frame protection circuit 5' can be shortened. Therefore, in this way, synchronization pull-in is made faster.

[Problem that the invention seeks to solve]

However, the above-described high-speed frame synchronization method has the problem that the number of frame bits increases and the amount of information that can be transmitted decreases.

[Means for solving problems]

The above problem, as shown in the principle block diagram of FIG. a frame periodic circuit 1 having a frame protection circuit 5 which shifts the frame signal when a signal is input and compares the frame signal in the comparison circuit 4; The receiving section includes an error correction circuit 2 which finds information for error correction of the input data and outputs an error detection signal if there is an error, and inputs the error detection signal to the frame protection circuit 5 as a mismatch signal. composition.

[Effect]

When there is no transmission path error, the fact that the error correction circuit 2 no longer issues an error detection signal means that frame synchronization has been achieved. Therefore, if this error detection signal that is generated when frame synchronization is not achieved is used as a frame synchronization mismatch signal for frame information, it will be equivalent to increasing the frame bits, and false synchronization will be less likely to occur.
We focused on the ability to shorten the rear protection time. Therefore, in the present invention, the error detection signal is sent to the frame protection circuit 5 as a mismatch signal to shorten the backward protection time so that the comparison circuit 4 can quickly establish frame synchronization. Therefore, synchronization can be achieved at high speed without increasing the number of frame bits, that is, without reducing the amount of information that can be transmitted.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of the main parts of the receiving section according to the embodiment of the present invention.

The difference in Figure 2 from Figure 3 is, for example,
In the case of Fig. 3, the frame signal used to be 2 bits per frame and 8 bits for 4 frames, but the frame signal is 1 bit per frame, 4 bits per frame.
There are four bits per frame, and the error detection signal of the error correction circuit 2 is input to the frame protection circuit 5 as a frame synchronization mismatch signal of frame synchronization information.

This different point will be explained below.

The error correction circuit 2 finds the block code part A based on the output from the AND circuit 3, and performs error correction.

At this time, if frame synchronization is not achieved, an error detection signal is output, which is sent as a frame synchronization mismatch signal to the frame protection circuit 5, and processing is performed as a frame synchronization mismatch.

Once frame synchronization is achieved, the error correction circuit 2 will hardly output an error detection signal unless a transmission path failure occurs.

In other words, using an error detection signal as a frame synchronization mismatch signal is equivalent to increasing the number of frame bits, so false synchronization is less likely to occur and the backward protection time can be shortened, which means that transmission is possible without increasing frame bits. It is possible to speed up synchronization pull-in without reducing the amount of information.

〔Effect of the invention〕

As explained in detail above, according to the present invention, there is an effect that synchronization pull-in can be made faster without reducing the amount of information that can be transmitted.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of the main part of the receiving section of an embodiment of the present invention, and FIG.
The figure is a block diagram of the main parts of a conventional receiving section, and FIG. 4 is a diagram showing the frame format of input data. In the figure, 1 and 1' are frame synchronization circuits, 2
is an error correction circuit, 3 and 7 are AND circuits with inversion,
4 and 4' are comparison circuits, 5 and 5' are frame protection circuits, and 6 and 6' are frame counters.

Claims (1)

[Claims] 1. A comparison circuit 4 which compares input data and a frame signal and outputs a mismatch signal to a frame protection circuit 5 if they do not match, and shifts the frame signal when a predetermined number of mismatch signals are input. The comparison circuit 4
A frame synchronization circuit 1 having a frame protection circuit 5 to be compared with the frame protection circuit 5 inputs the input data and a frame signal, finds information for error correction of the input data based on the position of the frame signal, and detects errors. A high-speed frame synchronization method characterized in that, in a receiving section having an error correction circuit 2 which outputs an error detection signal if any, the error detection signal is inputted to the frame protection circuit 5 as a mismatch signal.