JPH01190029A - Ad converter circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an AD conversion circuit called a serial-parallel system that converts upper and lower data by dividing them.

[Summary of the invention]

The present invention relates to an AD conversion circuit, and is capable of performing AD conversion with good linearity by expanding the conversion range of lower-order data and correcting upper-order data when converted within this expanded range.

[Conventional technology]

An AD conversion circuit called a serial-parallel method has been proposed, which converts upper and lower data by dividing them (Japanese Patent Laid-Open No.
8-9426).

[Problem to be solved by the invention]

However, in the above-mentioned circuit, if perfect matching is not performed between the circuit that converts the upper data and the circuit that converts the lower data, the linearity may deteriorate at the boundary between the upper data.

That is, in the above-described circuit, the same input signal must be supplied when converting upper-order data and when converting lower-order data. For this reason, methods such as sample-holding and supplying human input signals have been considered.

However, the sample-and-hold circuit cannot completely reduce signal fluctuations to zero, and therefore, for example, if there is a fluctuation in the increasing direction of the signal, a higher potential than when converting upper data will be applied to the converter of lower data. A signal may exceed the upper limit of the conversion range of the lower-order data at the boundary of the conversion of the upper-order data. In this case, the lower data remains at its maximum value, and for example, when a signal as shown by the solid line in Figure 4 is supplied, the variation width ΔV of sample and hold is shown at the boundary of the upper data as shown by the broken line in the figure.
distortion will occur.

This application was filed in view of these points.

[Means to solve the problem]

The present invention uses potentials taken out from predetermined connection points of a plurality of resistors (2,) to (2,,,) connected in series between arbitrary potentials (v, T, Vr8) to generate upper-level data. (comparator (3)), and converts the lower data using the potential taken out from the connection point of each resistor (switches (41) to (4□, 6)) in the range converted by the upper data. In an AD conversion circuit configured to perform AD conversion (comparator (5)), the conversion range of the lower-order data is expanded by a predetermined amount above and below the range converted by the upper-order data (switches (6,) to ( 62, 6)), and when the lower data is converted in this expanded range (error detection circuit (10,) to (102)), the converted value of the upper data is corrected (error correction circuit (8) )).

[Effect]

According to this, the conversion is performed at the upper and lower extensions of the conversion range of lower-order data, and the upper-order data is corrected using the conversion value at this extension, thereby reducing the distortion at the boundary of the upper-order data. is corrected, and A with good linearity
D conversion can be performed.

〔Example〕

In FIG. 1, (la) and (lb) are terminals to which the highest potential VrT and lowest potential VrB for AD conversion are supplied, and between these terminals (la) and (lb),
For example, in the case of 8-bit AD conversion, a series circuit of 256 resistors (21) to (2□, 6) having the same resistance value is provided in a zigzag pattern of 16 resistors each as shown in the figure.

Each of the series circuits of this resistor (21) to (2□ss)
The 155 points among the connections for each of the six resistors are connected to the comparator (3) of the upper data.

Also, one ends of the resistors (21) to (223,) arranged in the horizontal direction when arranged in the above-mentioned zigzag pattern are connected to each other in each column through the switches (41) to (42ss), respectively. , this connection middle point (166 points) is connected to the lower data comparator (5).

Furthermore, the other ends of the resistors (21) to (2□, 6) in the upper three rows and the lower two rows are connected to switches (6, 6), respectively.
) to (6□,) are connected to each other column by column, and the 5 dots in the middle of these connections) are the lower data comparators (5)
connected to.

Moreover, these switches (61) to (62,,) are arranged on the same line as the vertical arrangement of switches (4,) to (42ss) associated with resistors on opposite sides of each other in the folded part of the above-mentioned zigzag arrangement. established in In addition, in the top row, the switches for each folded part are connected in parallel, so
The arrangement shown is equivalent. Also, the terminal (la> (lb)
Resistors near (2,) to (2,) and (225,) to
For (2□, 6), there is no resistor on the opposite side of the fold, so switches (6□) (63) and (6
2,,) (625g) is not provided, and the switch (6,)
and (6□, 6) are considered valid.

Further, (7) is an input terminal for the signal potential Vin, and this input terminal (7) is connected to the comparators (3) and (5).

As a result, the comparator (3) first compares the human power signal potential Vin with the 16
The potential of each connection midpoint is compared, and a 15-bit comparison output is taken out. Note that the comparison output is taken out in such a manner that only one bit corresponding to the signal potential Van is at a high potential and all others are at a low potential.

This comparison output is supplied to a circuit (8) for encoding higher-order data forming a 4-bit digital code and for error correction (to be described later), and is also supplied to the above-mentioned switch (4,) according to this comparison output. ~(42s-) and (
The vertical columns from 6,) to (625,) are selected, and all the switches in the corresponding columns are turned on. The figure shows the case where the comparison output is obtained at the 2nd bit from the highest potential VrT side,
Switches in the second row from the right in the figure (4,,) ~ (432
) and (61s) (6, -) (632) (6
34) (6-s) is turned on.

Therefore, in this example, the comparator (5) has a resistor (2, s
) to the other end of (23,) are supplied, and these potentials and the signal potential Vin
are compared and a 21-bit comparison output is taken out.

Further, these comparison outputs are supplied to a lower data encoder (9) forming, for example, a 4-bit digital code, and switches (6, 2) (63,) (63
5) A comparison output corresponding to the potential from switch 1 (6) is supplied to the error detection circuit (OR circuit) (10,).
Comparison outputs corresponding to the potentials from ,,)(6,,) and (4,,) are supplied to an error detection circuit (OR circuit) (lO□). And these detection circuits (10,) (10
The signal from □) is supplied to the above-mentioned error correction circuit (8), and when there is a signal from the detection circuit (10,), “1” is added to the encoded value of the upper data, and the detection circuit (
When there is a signal from 10□), a correction is performed to subtract "l" from the encoded value of the upper data.

Further, the corrected encoded value from the correction circuit (8) is latched by the upper data latch circuit (11), and the encoded value from the encoder (9) is latched by the lower data latch circuit (12), These latched values are combined and taken out to the output terminal (13).

In this way, according to the above-mentioned circuit, conversion is performed at the upper and lower extensions of the conversion range of lower-order data, and the upper-order data is corrected using the conversion value in this extension, so that the boundary of the upper-order data is distortion is corrected, and AD conversion with good linearity can be performed.

In other words, in the above circuit, when the conversion range of arbitrary lower data is determined by the upper data, the comparator (5) receives potentials whose conversion range is extended above and below the original conversion range, as shown in FIG. is supplied. The encoded value of the encoder (9) for this conversion range is shown on the right side of the figure, and when the output of the comparator (5) from the high potential side extension section is obtained, the upper data is " By adding "1" and subtracting "1" from the upper data when the output of the comparator (5) from the low potential side extension part is obtained, for example, as shown on the left side of the figure, the boundary of the upper data AD conversion with good linearity can be performed even for the signal potential Vin.

Furthermore, FIG. 3 shows a time chart of the operation.

In this figure, when there is a signal potential Vin as shown in A, B is a clock signal and the comparator (
In 3), as shown in C, the signal potential Vl is sampled (S,) during the high potential period of 1 of the clock signal and combined (C,) during the low potential period. As a result, as shown in D, the upper data (
M D+ ) is formed.

Further, a switch is selected by the output of the comparator (3), and a potential (RVI) as shown at F is supplied to the comparator (5).

On the other hand, in the comparator (5), as shown in G, the signal potential V sampled (Sl) during the high potential period 1 of the clock signal is held (Sl) during the low potential period and the high potential period 2.
Hl) and compared during the low potential period of 2 (C1)
be done. As a result, the lower data (LDI) is formed during the high potential period 3 as shown in H, and the upper data is corrected (MD'+) as shown in E, and these correction data and Lower data is output (Out
+) to be done.

At this time, the next signal potential v2 is sampled (S,) as shown by C and G, and this operation is repeated thereafter.

In this way, AD conversion is performed with two clocks as one cycle. .

Note that in the above-described circuit, the signal potential to be converted corresponds to the hold value at the time of conversion of lower-order data. Therefore, the bias and the like are adjusted so that the hold value at this time becomes the required signal potential.

Furthermore, according to the circuit described above, the sample-and-hold circuit may have relatively low performance as long as the rate of variation is fixed, and furthermore, if the signal potential changes slowly, the sample-and-hold circuit can be omitted. be.

Furthermore, according to the above-mentioned circuit, control can be performed extremely easily by devising the switch arrangement.

〔Effect of the invention〕

According to this invention, conversion is performed at the upper and lower extension parts of the conversion range of lower-order data, and the upper-order data is corrected using the conversion values at these extension parts, so that the conversion at the boundary of the upper-order data is performed. Distortion has been corrected, and AD conversion with good linearity can now be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of the present invention, FIGS. 2 and 3 are diagrams for explaining the same, and FIG. 4 is a diagram for explaining the prior art. (la) (lb) is the potential terminal, (2) is the resistor, (3
) (5) Hacon balator, (4) (6) is a switch, (7) is a signal input terminal, (8) is an encoding and error correction circuit, (9) is an encoder, (10,) (10
□) is an error detection circuit, (11) and (12) are latch circuits, and (13) is an output terminal. Agent Paige Ito
Hide Matsukuma price data
Figure 2

Claims (1)

[Claims] A/D conversion of high-order data is performed using a potential taken out from a predetermined connection point of a plurality of resistors connected in series between arbitrary potentials, and the range converted by the above-mentioned high-order data is In an AD conversion circuit that performs AD conversion of lower-order data using the potential taken out from the connection point of each resistor, the conversion range of the lower-order data is set above and below the range converted by the upper-order data by a predetermined amount. The AD conversion circuit is configured to expand the conversion value of the upper data in the extended range, and to correct the converted value of the upper data when the lower data is converted within the expanded range.