JPS60197018A - A/d converter - Google Patents

Abstract

PURPOSE:To prevent a malfunction, and also to improve conversion accuracy by using a charge balanced type having sample holding function for a comparator, in a series-parallel type A/D converter. CONSTITUTION:Charge balanced type MOS comparators 16, 17 having sample function are used for converting high-order and low-order bits, respectively. Also, each terminal voltage of a voltage dividing circuit of a reference voltage VREF consisting of resistances R1-R16 is compared with an input voltage Vin. Subsequently, a result of comparison of a high-order comparator group 16 and a low-order comparator group 17 is converted to a high-order bit DU and a low- order bit DL by an encoder 18 and an encoder 19, respectively. Also, a latch 20 holds a result of comparison of the high-order bit, one of switch groups 12-15 is selected by this holding data, and comparing conversion of the low-order bit is executed. In this way, mismatching on a circuit operation in case of converting the high-order bit and the low-order bit is prevented, a malfunction is prevented, and also conversion accuracy can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an A/D converter, and particularly to a parallel A/D converter suitable for integration into an integrated circuit.

[Background of the invention]

The circuit scale of a parallel A/D converter that achieves high-speed A/D conversion increases exponentially with the number of bits, so the A/D converter shown in Figure 1, which belongs to the series/parallel type, The circuit can be simplified and is suitable for integrated circuits (Japanese Patent Laid-Open No. 57-13
Publication No. 1123).

This A/D converter compares the input voltage V+a with each divided voltage of the reference voltage VRyat which is resistance-divided by three comparators 10, determines the upper 2 bits DU via the encoder 18, and Based on the results, one of the four switch groups 12 to 150 is selected and turned on, and the reference divided voltage selected by the three comparators 11 and ■1
．． DL
Determine. This converter using 4 bits as an example is 150
Reference divided voltage and input voltage V1. Unlike a fully parallel A/D converter, which uses 15 comparators to compare the values simultaneously, three comparators determine the upper two bits, and then three other comparators determine the lower two bits. do. In general, in a 2n-pit A/D conversion, the upper n bits are determined by 211-1 comparators, and the lower n bits are determined by another 211-1 comparators. Therefore, the required number of comparators is 2"'-2, which is significantly smaller than 22n in the case of a fully parallel type. For example, 10 (n = 5)
In the case of bits, for 1024 fully parallel gifts,
It is sufficient to have 62 comparators.

By the way, the A/D converter shown in Fig. 1 uses separate comparator groups to determine the upper bits and lower bits, and performs comparison operations at different timings. Mismatches may occur. For example, when V + a approaches the reference divided voltage VRI, the comparator 10 (a
) changes so that the selected switch group (e.g. 12) changes during the conversion of the lower bits to the adjacent switch group (e.g. 1).
3) may cause an error. Furthermore, due to the difference in the arrangement of the upper comparator 10 and the lower comparator 11 on the integrated circuit or the difference in comparison time, the switch group (for example, 12) selected based on the comparison result of the upper bits may not be appropriate, and the switch group of the adjacent switch (eg 13) should be used for comparing the lower bits. These problems are unique to conventional A/D converters belonging to the series/parallel type, and are factors that often cause the converter to malfunction and degrade conversion accuracy.

[Purpose of the invention]

The purpose of the present invention is to solve the above problems, prevent mismatches in circuit operation in converting upper bits and lower bits, and
High-precision, malfunction-free series-parallel integrated circuit A/D
The purpose of the present invention is to provide a converter.

[Summary of the invention]

In order to achieve the above object, the present invention uses a charge-balanced comparator with a sample-and-hold function as a comparator, and provides a latch to hold the conversion result of the upper bit to stably select a switch group for lower bit conversion. At the same time, the circuit configuration is made to cover the above-mentioned mismatch by slightly increasing the number of comparators used for lower bit conversion and expanding the range of reference divided voltages to be compared up and down. As a result, it has become clear that a highly accurate and stable serial-parallel type integrated circuit A/D converter can be realized.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using examples.

FIG. 1 is a diagram showing the circuit configuration of an A/D converter according to the present invention. For simplicity, a resolution of 4 bits is used as an example. Charge-balanced MOS comparators 16 and 17, which essentially have a sample-and-hold function, are used to convert the upper and lower bits, respectively, and a reference voltage V R consisting of 16 resistors Rt-16 is used.
Each terminal voltage of the voltage dividing circuit of IF and the input voltage v1. Compare. Upper comparator group 16 and lower comparator group 1
7 comparison results are encoder 18 and encoder 1, respectively.
9, the upper bit DU, the lower bit D1. is converted to In addition, the latch 20 holds the comparison result of the upper bits,
With this retained data, one of the four switch groups 12 to 15
is selected, and the lower bits are compared and converted.

As shown in the figure, the operation of this A/D converter is to control the input and output of the inverter 21 of the electric M balanced type NIA V-inverter 16 by atzφ (high level) controlled by clocks φ and φ having opposite phases to each other. While short-circuiting, a reference divided voltage is input to each capacitor C.

Next, after opening the input and output of the inverter 21 of the charge-balanced comparator 16 by φ (Higtl level),
The input switch SW1 is switched to input the input voltage VIa to each capacitor C. As a result, the comparator 16 compares the reference divided voltage and the input voltage vIm, and the comparison output is converted via the encoder 18 into the upper two bits of digital 1fiDu. At the same time, the comparison output is converted into predetermined data Dszx via the decoder 18, and stored in the shutter 20 according to the next clock φ. On the other hand, the charge-balanced converter 17 short-circuits the input and output of the inverter 220 due to φ (high level), and also applies the input voltage 1 to each capacitor C. Enter. Next, φ(Hight
l level), the inverter 22 of the comparator 17
After opening the input/output of the capacitor, the input switch 8W2 is switched to input the reference divided voltage to each capacitor. At this time,
One of the four switch groups 12 to 15 is driven by the data DggL stored in the latch 20, and the corresponding reference divided voltage is selected. As a result, the comparison output of the comparator 17 is the digital value D of the lower two bits via the encoder 19.
Converted to L.

Charge-balanced comparators inherently have a sample-and-hold function, so that the same sample input voltage V1. are compared respectively. Since the conversion result of the upper bits is held by the two switches 20, one of the switch groups (12 to 15) is stably selected when converting the lower bits, which is different from the conventional A/D.
Malfunctions that were a problem with the converter (FIG. 1) are prevented.

Further, the A/D converter of the present invention has an A/D converter with a frequency of clock φ.
Can perform D conversion. Therefore, 15 charge-balanced comparators simultaneously detect the input voltage V1. Compare with 4
The conversion speed is the same as that of a completely parallel type A/1) converter of bits, and a high-speed A/D converter can be realized. Since the number of comparators is significantly reduced and the circuit configuration is simple, it is suitable for integrated circuit implementation.

FIG. 3 is a diagram showing another embodiment of the A/D converter of the present invention. Charge-balanced comparators 16, 1 as in FIG.
7.Resistance voltage divider circuit for reference voltage MRzy (Rs to Ig)
, encoders 18, 19, switch groups 23 to 26, 2, and logic circuit 27. Of these, switch groups 23 to 26 are made up of seven switches by adding four switches to each, and four comparators are also added to the Koniper V-PXR used for converting lower pits, making seven comparators. . The encoder 19 inputs the comparison results of these comparators 17 and outputs the 3-bit lower data D.
'Output L. The upper 2-bit converted data Do and the lower-order data Dj are input to the logic circuit 27 and processed to obtain a 4-bit digital converted value.

The operation of this A/D converter is controlled in the same way as shown in Fig. 2 by locks φ and φ, which have opposite phases to each other, and the conversion of upper bits and lower pits is performed alternately, and a digital conversion l0iD of input voltage V Im is obtained. It will be done. In converting lower pits, the range of reference divided voltages compared is extended upward and downward, so any mismatch between the upper bit conversion circuit and the lower pit conversion circuit can be corrected, and correct conversion results can be obtained. .

For example, because the accuracy of the upper comparator 16 is low, the switch group 24 is selected instead of the switch group 24.
Suppose that 3 has been selected. Even in this case, if the input voltage V Ia is less than the terminal voltage of 21 points, switch group 2
The reference divided voltage selected by V1.3 and the input voltage v1. can be effectively compared to obtain the correct digital conversion value. In this case, since the lower data D'L, which should originally be 2 bits, becomes 3 bits due to overflow, the 1 bit of overflow can be carried to the upper bit (Du). This process can be easily realized by the logic circuit 27. On the other hand, suppose that the upper comparator 16 selects the switch group 24 when it should have selected the switch group 23.

Even in this case, the input voltage ■1. If the voltage is greater than or equal to the terminal voltage at 22 points, the comparison with the reference divided voltage can be made effectively, and a correct digital conversion value can be obtained. In this case, since the lower data D'L is represented by 3 pits by an angle (negative number), the digital converter can be obtained by simply adding or subtracting the upper 2 bit data Du and the lower 3 bit data DL using the logic circuit 27. It will be done.

〔Effect of the invention〕

As described above, according to the present invention, series-parallel type A/I)
In the converter, mismatches in circuit operation between upper bit and lower bit conversion can be prevented, and a high-speed A/D converter with high accuracy and no malfunction can be integrated into an integrated circuit.

Furthermore, the circuit configuration is complete, the circuit scale is small, a high-resolution, high-speed A/D converter can be realized in a small area, and the power consumption is small, so the effects are outstanding in terms of performance and economy.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the circuit configuration of a conventional series/parallel type A/D converter, and FIGS.
It is a figure which shows the example of a circuit structure of a converter, and a time chart. FIG. 3 shows another example of the circuit configuration of the A/D converter of the present invention. 10.11... Comparator, 12-15... Switch group, 21.22... Inverter, 23-26...
・Switch group. Agent Patent Attorney Akio Takahashi”4 1 mouth ■ Z Figure It)

Claims (1)

[Claims] 1. A resistor string consisting of a plurality of resistors connected in series, and a first comparator group that respectively compares a first divided voltage group divided by the resistor string with an input terminal. , the first
a first encoder that encodes a comparison result of a group of comparators; controlled by the output of the first encoder;
A switch lever for selecting a second divided voltage group divided by the resistor string, and a second switch selected by the switch group.
In an A/D converter, the A/D converter includes a second group of comparators that compare input terminals with a group of divided voltages of ta'x and a second encoder that encodes the comparison results of the second group of comparators. , a capacitor, a means for alternately applying the divided voltage and the input terminal to one end of the capacitor, an inverter whose input terminal is connected to the other end of the capacitor, and an inverter for each comparator of the second comparator group. It consists of a comparator consisting of a switch whose one end is connected to the input end and the other end is connected to the output end of the inverter, the output of the first encoder is input to a storage circuit, and the output of the storage circuit is used to connect the switch group. An A/D converter that controls. 2. In the A/D converter according to claim 1,
The first group of comparators determines two divided voltages including the input voltage from the first group of divided voltages, and the second group of comparators determines the two divided voltages including at least the two divided voltages. An A/D characterized in that the second divided voltage group is a voltage obtained by dividing the piezoelectric voltage by the resistor array.
converter.