JPH0119112B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timepiece circuit with a load compensation function.

The load compensation function in watches attempts to make the power supply battery smaller, thinner, and have a longer lifespan by driving the step motor that drives the watch mechanism with as little power as possible. The time width of the drive signal is cut down to a state with little energy margin, and instead, the operation of the motor is constantly checked. (This can occur when the load increases during driving or when the internal resistance of the power supply battery increases due to a drop in the environmental temperature), an additional drive signal with a wider width is immediately output to overcome the increased load torque and perform step operation. This idea is well known. However, testing of circuits for this purpose has conventionally been difficult because the testing equipment has devised ways to generate the necessary signals, as will be described later.

In the present invention, by adding a simulated load circuit to the circuit on the watch side, it is possible to eliminate the need for modifying the test equipment, reduce the cost required for testing, and provide a means for increasing the reliability of functional operation. Its purpose is to

In order to clarify the circumstances surrounding circuit testing, we will begin by providing a detailed explanation of conventional load compensation techniques, especially in terms of circuits. Figure 1 is an example of a block diagram of a conventional watch.
The output of the oscillation circuit 1 is applied to a frequency dividing circuit 2, and the output of the frequency dividing circuit 2 is applied to an output control circuit 3.
A load is connected to the output terminals A and B of the output control circuit 3, and the load is specifically, for example, a step motor 4, and the time indicating device 6 is driven by the motor 4. The output terminals A and B are connected to a load state detection circuit 7, and the load state detection circuit 7
The output of is connected to the output control circuit 3.

The operation of the timepiece shown in FIG. 1 is as follows. When a 1 second period signal and a signal with a shorter period are applied from the frequency dividing circuit 2 to the output control circuit 3, the output control circuit 3 creates a drive output signal based on these signals, but the drive output Normally, output terminals A and B are both at a low potential (hereinafter abbreviated as "L"), and every second, output terminals A and B are alternately at a high potential for a short time (hereinafter abbreviated as "H"). become.
Therefore, currents in opposite directions alternately flow through the coil 5 for a short time every second. The motor 4 is driven by this current, but since the drive output signal is terminated before the motor 4 rotates a predetermined rotation angle, the motor 4 continues to rotate due to inertia after the drive output signal is terminated, and eventually the motor 4 When reaches a certain rotation angle,
Thereafter, it oscillates damped and stops at a predetermined rotation angle. The back electromotive force induced in the coil 5 during the damped vibration of the motor 4 well indicates the state of movement of the motor 4, and therefore can be used to confirm whether the motor 4 rotates normally. Specifically, detection is performed by checking the direction of the back electromotive force generated after a certain period of time has elapsed after the drive output signal was discontinued. The output terminals A and B are both fixed at "L" until immediately before this detection is performed (the period after the drive output signal is discontinued until the detection is performed), and the coil 5 is in a short-circuited state. A current flows through the coil 5 due to the back electromotive voltage.

Next, when either output terminal A or B is set to an open state at the time of detection, the current that was flowing through the coil 5 immediately before it was set to the open state will be discharged from the coil end connected to the output terminal that has been set to the open state. A voltage corresponding to the direction and magnitude appears, the magnitude or direction of this generated voltage is determined by the load state detection circuit 7, and a determination result as to whether the motor 4 is operating normally is provided to the output control circuit 3. It will be done. If it is determined that the motor 4 does not rotate normally, the output control circuit 3 again controls the coil 5.
Give a drive output signal to. The drive output signal at this time is configured so that more power is applied to the coil 5 than a normal drive output signal, and the motor 4 is ensured to rotate by this drive output signal.

Next, the configuration of the circuit portion of the output control circuit 3 and the load state detection circuit 7 will be explained in detail based on the circuit diagram of FIG. 2.

In FIG. 2, 8 is a circuit portion showing a part of the output control circuit 3, and 7 is the load state detection circuit. In FIG. 2, SP is a signal corresponding to a normal drive output signal, FP is a signal corresponding to a drive output signal that is additionally applied when the motor 4 does not rotate normally, and ST is a signal that provides timing for detecting the rotational state of the motor 4, and is specifically expressed as voltage waveform signals of the signals SP, ST, and FP shown in the time chart of FIG. Signal SP, FP, ST
is created by the waveform shaping circuit section in the output control circuit 3 using the signal supplied from the frequency dividing circuit 2. Regarding this section (waveform shaping circuit section), are not particularly related to the present invention and are therefore not shown. The signal SP is applied to one input terminal of the OR gate 11 and the input terminal of the inverter 29. The output terminal of the inverter 29 is connected to one input terminal of the NAND gate 23, and the output terminal of the NAND gate 23 is connected to one input terminal of the AND gate 10 and one input terminal of the NAND gate 24. The output terminal of the NAND gate 24 is connected to the other input terminal of the NAND gate 23 and one input terminal of the NOR gate 9. The signal ST is applied to the remaining input terminal of the NOR gate 9, and the output terminal of the NOR gate 9 is applied to the NAND gate 1.
3, 16, and 25, respectively. The signal FP is connected to an input T of a falling-triggered toggle flip-flop 12 and to the other input of the AND gate 10. The output terminal of the AND gate 10 is connected to the remaining input terminal of the OR gate 11. The output terminal of the OR gate 11 is connected to one input terminal of each of NAND gates 14 and 15. One output terminal Q of the flip-flop 12 is connected to the remaining one input terminal of each of the NAND gates 13 and 14, and the other output terminal is connected to the remaining one input terminal of each of the NAND gates 15 and 16. Ru. The output terminal of the NAND gate 14 is connected to the gate terminal of the P channel transistor 20 and one input terminal of the AND gate 17. The output terminal of the NAND gate 15 is connected to the gate terminal of the P channel transistor 21 and one input terminal of the AND gate 18. The AND gates 17 and 1
The remaining input terminals of each of the gates 8 are connected to the output terminals of the NAND gates 13 and 16, respectively,
The output terminals of AND gates 17 and 18 are connected to the gate input terminals of N-channel transistors 19 and 22, respectively. The drains of the P-channel transistor 20 and the N-channel transistor 19 are commonly connected to the output terminal A, and are also connected to the input terminal of the inverter 28. The drains of the P-channel transistor 21 and the N-channel transistor 22 are commonly connected to the output terminal B and to the input terminal of the inverter 27. The two input terminals of the NAND gate 26 are connected to the output terminals of the inverters 27 and 28, respectively, the output terminal of the NAND gate 26 is connected to the remaining input terminal of the NAND gate 25, and the output terminal of the NAND gate 25 is connected to the output terminal of the NAND gate 24. is connected to the remaining input terminal of Furthermore, transistor 20
The sources of transistors 19 and 21 are commonly connected to a power supply potential (Vdd), and the sources of transistors 19 and 22 are commonly connected to a power supply potential (Vss).

The operating waveforms of the circuit shown in FIG. 2 are shown in the time chart of FIG. 3. Now, if the potential of one output terminal Q of the flip-flop 12 is logically "H" in the state before time t1, the output terminal becomes "L".
Therefore, the outputs of the NAND gates 15 and 16 are both "H", and the AND gate 18 receives both output signals of the NAND gates 15 and 16 as inputs.
Since the output of is also "H", the P channel transistor 21 is off and the N channel transistor 22 is on. Therefore, the output terminal B is constantly fixed at the Vss level, that is, "L".
Also, at this time, the output signals of the NAND gates 13 and 14 take "H", and the output signal of the AND gate 17 also takes "H", so the transistor 19 is on, the transistor 20 is off, and the output terminal A is "L". "It is in. Next, at time t1, when the signal SP changes from "L" to "H", this signal SP goes to the OR gate 1.
1. Turn on the transistor 20 via the NAND gate 14 to set the potential of the output terminal A to "H".
Therefore, current flows through the coil 5 from the output end A to the output end B, and the motor 4 rotates. Next, time t
2, when the signal P5 of the NAND gate 24 is "L" and the signal ST is "H", the signal SP changes from "H" to "L"
Then, the signal SP passes through the OR gate 11 to turn off the transistor 20 in order to make the output of the NAND gate 14 "H", and also causes the "L" output of the OR gate 11 and the "H" output of the NAND gate 14 to become "H". The "H" output of the NAND gate 13 causes the signal P3 of the AND gate 17 to go "H", so the transistor 19 turns on and output terminal A goes "L".
Make it. Therefore, the motor 4 continues to rotate due to inertia, and the back electromotive force generated at this time causes current to flow through the coil 5 via the N-channel transistors 19 and 22 which are in a short-circuited state. Next, at time t3, the signal
When ST changes from “H” to “L”, Noah Gate 9
The output signal P6 of the NAND gate 13 is set to "H", the output signal P7 of the NAND gate 13 is set to "L", and the output signal P3 of the AND gate 17 is set to "L".
9 is turned off, and the output terminal A becomes open. At this time, a positive or negative voltage is generated at the output terminal A depending on the direction of the current flowing through the coil 5 immediately before. If the motor 4 is rotating sufficiently and a positive voltage exceeding the threshold voltage of the inverter 28 is generated, the output signal P8 of the inverter 28 becomes "L", and the output of the NAND gate 26 Signal P9 becomes “H”,
Furthermore, at time t3, since the signal ST and the signal P5 are both "L", the output signal P6 of the NOR gate 9 becomes "H", and the output signal P1 of the NAND gate 25 becomes "H".
0 becomes "L". On the other hand, Nand Gate 23 and 2
Reference numeral 4 constitutes a set-reset type flip-flop, and this flip-flop activates the inverter 2 in advance at the time t1 when the signal SP becomes "H".
The output signal P4 of the NAND gate 23 is set to "H" through the gate 9. If the motor 4 rotates correctly, the output signal P10 of the NAND gate 25 becomes "L" at the time t as described above.
3, the output signal P4 of the NAND gate 23 is reset to "L". Therefore, in the reset state where the output signal P4 of the NAND gate 23 is "L", even if the signal EP changes from "L" to "H" at time t5, the AND gate 10 is turned off by the "L" signal P4. Since the passage of the signal FP is prohibited, no change occurs in the logic state within the circuit portion 8, and the toggle flip-flop 12 is activated only at time t6 when the signal FP changes from "H" to "L". The output Q of is inverted from "H" to "L". Therefore, when the toggle flip-flop 12 is inverted at time t6, the signal P6 of the NOR gate 9 takes "L";
The signal P7 of the NAND gate 13 is "H", the signal P2 of the NAND gate 14 is "H", the NAND gate 15
The output signal of the NAND gate 16 is set to "H", and the output signal of the AND gate 18 is set to "H". As a result, the coil 5 is brought into a short-circuited state by turning on transistors 19 and 22 and turning off transistors 20 and 21, thereby setting both output terminals A and B to "L". Note that in this short-circuit state, the next signal SP that takes "H" arrives, turns on transistors 19 and 21, and turns on transistors 20 and 22.
Turn off the coil 5 from output end B to A.
The drive current is maintained until the motor 4 rotates. Next, the time chart in FIG. 3b shows a case where the motor 4 does not rotate correctly. still,
The operation of the circuit portion 8 from time ta to time tb is as follows.
Since the operation is exactly the same as the operation from time t1 to time t2 described in FIG. 1A, the explanation of this operation will be omitted. At time tc, when the signal ST changes from "H" to "L", the signal P6 of the NOR gate 9 goes "H".
The output signal of AND gate 10 is "L", the signal P1 of OR gate 11 is "L", flip-flop 1
The output signal Q of the AND gate 17 is "H", the signal P7 of the NAND gate 13 is "L", the signal P2 of the NAND gate 14 is "H", and the signal P3 of the AND gate 17 is "H".
As a result, the transistor 19 changes from an on state to an off state, and the transistor 20 remains off, so that the output terminal A becomes an open state.

Furthermore, at this time tc, the output signal of the NAND gate 15 is "H", the output signal of the NAND gate 16 is "H", and the output signal of the AND gate 18 is "H", so the transistor 21 continues to be in the off state and the transistor 22 remains on. As a result, the output signal of the inverter 27 remains "H", and at this time, the motor 4 does not rotate sufficiently, and the inverter 28 is output from the coil 5.
Since no induced voltage exceeding the threshold voltage is generated, the signal P8 of the inverter 28 remains at "H". Therefore, the signal P9 of the NAND gate 26 continues to be "L" and the signal P10 of the NAND gate 25 continues to be "H", making it impossible to reset the flip-flop constituted by the NAND gates 23 and 24. That is, the signal P4 of the NAND gate 23 continues to be in the "H" state.

Next, at time te from this state, the signal FP changes from "L" to "H", and the AND gate 1
The output signal of 0 is set to "H". Moreover, at this time,
Since the signal P6 of the NOR gate 9 is "L" and the output signal Q of the flip-flop 12 is "H", the signal P7 of the NAND gate 13 is "H", the signal P2 of the NAND gate 14 is "L", and the output signal of the AND gate 17 is "H". becomes "L", so the transistor 19 is turned off, the transistor 20 is turned from off to on, and the output terminal A is given the potential of Vdd, that is, "H". Moreover, at this time te, the output signal of the NAND gate 15 is "H", the output signal of the NAND gate 16 is "H", and the output signal of the AND gate 18 is "H", so the transistor 21 is in the off state and the transistor 22 is in the off state. It is in the on state and the output terminal B is given the potential of Vss, that is, "L". As a result, a drive current flows through the coil 5 from the output terminal A to the output terminal B, driving the motor 4. At this time, since the conduction time of the drive current flowing through the coil 5 (period from time te to tf) is equal to the pulse width of the signal FP, the pulse width of the signal FP is set in advance.
SP pulse width (period from time ta to time tb)
By setting the motor 4 sufficiently wide,
Even if the motor 4 does not rotate correctly with the drive current given in the period from time ta to time tb as the load increases, the motor 4 can be rotated correctly with the wide range of drive current given in the period from time te to time tf. becomes possible.

The above is a circuit diagram showing the conventional configuration and its operation. Conventionally, when inspecting an integrated circuit with such a load compensation function without connecting it to a load such as a motor, a fairly complicated procedure was required. . The reason for this is that the load compensation function is related not only to the circuit for that purpose but also to the operation of the electric-mechanical system, including the step motor and its mechanical load, and is a function that operates when there is an abnormality in the system. Unless such a system is configured and an abnormal state is intentionally created in the mechanical system (for example, by applying a brake to the rotor), the state for inspection cannot be created. This is due to the circumstances. If you assemble the electrical-mechanical system and also add a mechanical brake mechanism and its operation means, you will need to manufacture a new mechanical system even if you are just testing the circuit, which will be costly and require a short inspection time. I won't be able to finish it. In particular, check ICs at the silicon wafer stage early,
Feedback of results to the manufacturing process becomes difficult. Therefore, as an alternative, it may be possible to substitute the response of the mechanical system with an electrical signal given from the outside, but even in that case, the signal generation circuit for that purpose would need to be incorporated into the inspection equipment, which would require some modification of the equipment, and the test program As the process becomes more complex, there is a problem in that the preparation stage for inspection becomes longer, even if it is not enough to require the manufacture of a mechanical system. Furthermore, if you test the device without making any changes to the hardware, even if it is logically determined to be a good product during the test, it may not work properly when a load such as a motor is actually connected. There was a risk of contamination.

Therefore, the present invention solves the above problem by providing a simulated load circuit within the integrated circuit, and the configuration thereof is shown below with the circuit diagram of FIG. 4.

Note that FIG. 4 partially shows a configuration in which a simulated load circuit D is added to the circuit portion 8 in FIG. The constituent elements described in
Other circuit components omitted in the figure are the same circuit components as in FIG.

In FIG. 4, the configuration of the simulated load circuit D is as follows. P channel transistor 3
0 and 31 are connected in parallel to the P-channel transistors 20 and 21, respectively, and the respective gate input terminals of the P-channel transistors 30 and 31 are connected to the respective output terminals of NAND gates 32 and 33, respectively. The NAND gates 32 and 3
One input terminal of each of the terminals 3 is commonly connected to the control terminal C. The output terminal of the NAND gate 13 is connected to the NAND gate 32 via an inverter 34.
is connected to the other input terminal of the Further, the output terminal of the NAND gate 16 is connected to the remaining input terminal of the NAND gate 33 via an inverter 35.

The operation is as follows. When the potential of the control terminal C is "L", the outputs of the NAND gates 32 and 33 are both "H", so the transistors 30 and 31 are constantly off, and therefore the output terminals A and B
If the coil 5 is not connected to the inverter 27, the output of the inverter 27 will be "L" at the time tc when the signal ST is "L" because the transistor 22 is in the on state and the output terminal B is "L" as described above. When set to "H", output terminal A is connected to transistors 19, 20 and 30.
Since the inverter 28 is in an open state and no induced voltage is applied because the coil 5 is not connected, the output signal P8 of the inverter 28 becomes "H", and the load is reduced as if the motor 4 did not rotate normally. The state detection circuit 7 performs a detection operation and operates the output control circuit 3. On the other hand, control end C
When the potential of the transistor 1 is "H", for example, at time tc when the output signal P7 of the NAND gate 13 becomes "L", the output terminal A of the transistor 1 is turned off.
9 and 20, the output of the NAND gate 32 becomes "L" due to the potential of the control terminal C, and the P channel transistor 3
0 is on, the output terminal A is pulled to "H", and the output of the inverter 28 becomes "L", and the load state detection circuit 7 performs the detection operation as if the motor 4 was rotating normally. and the output control circuit 3 is operated. As described above, according to the present invention, by setting the potential of the control terminal C to "H" or "L" and operating the simulated load circuit D, the load state can be detected even if the coil 5 of the motor 4 is not connected. The operation of the circuit 7 and the output control circuit 3 can be easily inspected.

Another feature obtained by implementing the present invention is that leakage of the N-channel transistors 19 and 22 can be checked logically. That is, when the coil 5 of the motor 4 is actually connected and the circuit is operated, even if the output terminal A is opened at time tc and the voltage from the coil 5 of the motor 4 is to be detected, if the N-channel transistor 19 If there is large leakage in the voltage, this voltage will go undetected. Therefore, when testing without connecting the coil 5 of the motor 4, it was necessary to measure the leakage of the N-channel transistors 19 and 22 using an analog method, but according to the present invention, the leakage of the P-channel transistors 30 and
By appropriately selecting the on-resistance of the N-channel transistors 19 and 22, the presence or absence of leakage in the N-channel transistors 19 and 22 can be checked logically to determine whether the circuit operation is normal or abnormal. That is, this is done by setting the control terminal C to "H" with the coil 5 disconnected, and logically measuring the presence or absence of voltages at the output terminals A and B at time tc. Of course, the P channel transistor 3
As the on-resistance of 0.31 is increased, even small leakage can be detected. However, if the on-resistance is increased too much, the time constant with the capacitance floating at the output terminal A or B becomes large, making it difficult to perform high-speed inspection.

As described above, according to the present invention, by simply adding a simple simulated load circuit, testing can be easily performed even without a load, and the test results are highly reliable, thereby increasing the reliability of the final product. The effects of implementation are very large.

In the description of the present invention, the motor 4 is used as a load.
The load is not necessarily limited to the motor. It may be something like a solenoid, or it may be not only an inductive load but also a capacitive load. In the case of a capacitive load, it is clear that the present invention can be applied to a circuit (not explicitly shown) that controls an output signal by detecting the charging or discharging level of a capacitor.

In addition, in FIG. 2, the case where the output terminals A and B are normally "L" has been explained, but the output terminal A
Naturally, if B and B are normally at "H", the method of connecting the simulated load will change.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an example of a conventional watch.
FIG. 2 is a circuit diagram specifically showing the circuit portion shown in FIG. 1, FIG. 3 a and b are time charts showing operating waveforms of the circuit in FIG. 2, and FIG. 4 is an embodiment of the present invention. FIG. 1... Oscillation circuit, 2... Frequency dividing circuit, 3... Output control circuit, 4... Motor (load), 5... Coil,
6...Time display device, 7...Load condition detection circuit,
8... Circuit part, A, B... Output end, C... Control end, D... Simulated load circuit.

Claims (1)

[Claims] 1. A drive output terminal that outputs an output signal to a connected load, and after driving the load, at least one of the drive output terminals is set in a floating state by a predetermined detection timing signal, and the load is A load comprising: a load state detection circuit that detects a generated potential state and outputs a pass/fail of the drive state of the load as a detection result; and an output control circuit that controls the state of the output signal based on the detection result. The circuit for a watch with a compensation function includes a test control terminal for testing the load compensation function in a state where the load is not connected, and the control terminal input and the detection timing signal are inputted.
It has a gate circuit having an AND function, and a switching means whose one end is connected to the drive output terminal and the other end is connected to a predetermined potential, and which is opened and closed by the output of the gate circuit, and a test signal is applied to the control terminal. and when the detection timing signal is active, the drive output terminal in the floating state is forcibly short-circuited to a predetermined potential, thereby simulating the potential state in which the load is expected to occur. A watch circuit with a load compensation function, characterized by having a simulated load circuit applied to a detection circuit.