JPH01196639A - Information processor - Google Patents

Abstract

PURPOSE:To reduce a processing step and execute garbage collection at a high speed by providing a register and a selector in a hardware for flag bit for garbage collection. CONSTITUTION:An information processor is equipped with a flag bit value register 21 for garbage collection GC, which holds a value to the flag bit for GC of a register for writing and reading to a main storage 1, and a selector 22 to write the contents of a bit, which is designated by the register to be designated at the time of a writing instruction to the main storage 1, to the flag bit. Accordingly, in case of the special writing instruction, by using the selector 22, over-writing is executed the flag bit for GC based on a micro- program is over-written with the contents of the flag bit value register 21 for GC and written to the main storage 1. Then, the writing of the GC flag bit of the high using frequency can be executed at a GC executing time. Thus, the processing step can be reduced and the GC can be executed at the high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to control of a main storage device in an information processing device.

[Conventional technology]

FIG. 2 shows a conventional information processing device of this type. In the figure, (1) is a main memory control unit that reads and writes data to and from the main memory; Equipped with a data register (5) for writing and reading data to the main memory (4), an address register (6) for specifying the main memory address when writing and reading data to the main memory (4), When writing data to (4), the data to be written is stored in the data register (5), and the address on the main memory to be written is stored in the address register (6).
When reading data, specify the address on the main memory to be read in the address register (6), and execute the read instruction, so that the data at the specified address is written to the data register. (5).

In addition, (2) is ALtl (Arithmetic Lo
gic is an arithmetic unit that performs operations such as addition/subtraction, logic, and shifts between registers using arithmetic unit (8), and this arithmetic unit (2) is a register file that is a high-speed access memory with a sport read function. (7), 8 LU (
8), comprises a comparator (9) that compares the tag value of source 1 and the tag value of source 2, and register file (7)
By writing operand data into a predetermined register and executing an ALU manipulation instruction, the result is written to a predetermined register (specified by the instruction) or a flag in the ALU (8).

However, the information processing device with the illustrated configuration uses a microprogram to control the hardware, and the register (7)
A program (called a microprogram) built into the hardware connects hardware function modules such as ALU (8) and controls the data flowing through them, and (3) executes this microprogram. This sequence control unit (3) includes a tag branch table (10) for searching the table based on the tag value to obtain a branch address, and a micro address generator ( 11), micro program counter (12),
Microinstruction register (13), WO2
(Writable (:ontrol 5tore)
(14), WO2 (14) stores a microprogram, its execution address is generated by a microaddress generator (11), and at this time, the microprogram counter (12) contains the address of the microinstruction being executed, Microinstruction register (
13) respectively hold microinstructions. Also,
(15) is the destination bus, (ia) is the destination tag bus, (17) is the source 1 tag bus, (18) is the source 2 tag bus, (19) is the source 1 bus, and (20) is the source 2 bus. .

In the above configuration, when the logical language is executed, structure data etc. are dynamically generated on the main storage device (4). However, each piece of data in the main memory (4) that is generated one after another by program execution often becomes unnecessary after a certain point in program execution. For this reason, in a logic language processing system, a function to collect main storage areas that are no longer needed during the execution of these programs, that is, a garbage collection (hereinafter referred to as GC) is essential. The method for implementing this GC is to mark the GC flag bit of the main memory cell that holds the necessary data to be left after GC, and then remove unnecessary data and transfer only the marked cells to the main memory. (4) There is a method to match one end of the above address.

In this method, the process of marking the GC flag bit is G
Since the frequency of C processing is high, high speed is required.

In the conventional hardware configuration, registers (5) and (7)
) and set the value of the GC flag bit in register (5) using ALU (8), then the main memory (
4) was written. For example, if you write 1 to register (5), write 2 to register file (7), and execute the microinstruction "Add these and write the result to register (5)," registers (5), (7) The gate opens and the buses (19) and (20) pass through to ALtl.
Data enters (8), addition is performed in ALU (8), the result is output to bus (15), and the gate of register (5) is opened again and written.

[Problem to be solved by the invention]

Since the conventional information processing device was configured as described above, the value of the flag bit had to be set before a write command, which was an obstacle to increasing the speed of GC processing.

This invention was made to solve the above-mentioned problems, and aims to provide an information processing device that can perform high-speed GC by eliminating the processing step of setting the value of a flag bit. .

(Means for Solving the Problems) An information processing device according to the present invention is an information processing device provided with one or more flag bits per word on a main storage device, and a register for writing to and reading from the main storage device. A garbage collection flag bit value register that holds the value for the garbage collection flag bit of , and a selector for writing the contents of the specified bit of the register specified at the time of a write instruction to the main storage device to the flag bit. It is.

[Effect]

According to the information processing device of the present invention, in the case of a special write instruction, by using the selector, the <GC flag bit is overwritten with the contents of the garbage collection flag bit value register based on the microprogram, and the main storage GC flag bits that are frequently used during GC execution can be written without using ALtl.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIG. 1, in which the same parts as in FIG. 2 are denoted by the same reference numerals. In Figure 1, (21) is a register that holds the value for the GC flag bit of the register for writing and reading into the main memory (4), and (22) is the register that holds the value for the GC flag bit when writing to the main memory (4). The GC flag bit of the register (21
) is a selector that controls whether to rewrite the value of the register (5) or the value of the register (5) based on the instructions of the microprogram, and is information with one or more flag bits per word on the main memory (4). In the processing device, the contents of a specified bit of a register specified at the time of a write instruction to the main memory (4) can be written to the flag bit. The rest is the same as the conventional example.

In the case of a normal write instruction, the contents of the register (5) including the GC flag bit are written to the address of the main memory (4) specified by the address register (6), but in the above configuration, In the case of a special write command, the selector (22) is used to set the <GC flag bit to the register (2) based on the microprogram.
The contents of 1) can be overwritten and written to the main storage device (4).

For this reason, in the horizontal microprogram method, which controls each part of the hardware by dividing the microinstruction into several fields and decoding them, each part of the hardware can be directly controlled with one microinstruction, for example. , ■ Read data from main memory (4), ■ Perform operations between registers using ALtl (8), ■ Conditional branch depending on register value, etc.
, is possible with conventional Tubertoware, but the word length of microinstructions becomes long, making programming difficult, and
When writing the flag bit for C, the ALU is used, so operations between other registers cannot be performed within the same one microinstruction cycle, and the number of microprogram steps increases, and as the number of steps increases, processing time naturally increases. However, in this embodiment, by providing the register (21) and selector (22) in the hardware for the GC flag bit, it becomes possible to rewrite the GC flag bit without using the ALU (8).

〔Effect of the invention〕

As described above, according to the present invention, the hardware configuration is such that writing of frequently used GC flag bits during GC execution is performed without using an ALU, so that
By increasing the horizontality of the horizontal microprogram, steps can be reduced, making it possible to realize faster GC.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. In the figure, (1): Main memory control section, (2): Arithmetic section, (3)
Nijiken control unit, (4): Main memory, (5): Data register, (6) Near address register, (8):
ALU, (21): Gc rough flag bit value holding means (
22): Selector. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] In an information processing device that has one or more flag bits per word on the main memory, a garbage collection flag bit value register that holds the value for the garbage collection flag bit in the write/read register to the main memory. An information processing device comprising: a selector for writing the contents of a specified bit of a register specified at the time of a write instruction to a main memory into the flag bit.