JPH0561669A - Semiconductor calculating device and electronic apparatus - Google Patents

Abstract

(57) [Abstract] [Purpose] In the case of program branching in a microcomputer with a large memory space, conventional microcomputers provided only short branch instructions or in-page branch instructions as conditional branch instructions. The present invention is
The purpose is to enable execution of a long branch or an out-of-page branch for all branch instructions such as conditional branch instructions, thereby increasing the degree of freedom in programming. [Configuration] In addition to a program counter 5 for designating an address of the program memory 1 and a page designating register 4, a new page register 6 is set. Before the branch instruction is executed, the branch destination page is written to the page specification register, and when the branch instruction is executed, the data in the new page register is transferred to the page specification register, enabling out-of-page branching for all branch instructions. To do.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address system for executing a branch instruction of a microcomputer.

[0002]

2. Description of the Related Art In a conventional microcomputer, a branch instruction is generally executed by describing a branch destination address or a relative address in an operand portion and branching. Therefore, a microcomputer that can set a large address space has two types of branch instructions with different address widths that can be branched. Instructions that branch with a short address width are short branch instructions, and instructions that branch with a long address width are long branch instructions. Was called.

For example, Hitachi 8-bit microcomputer H
8 adopts a method of managing a memory for each page with an address space of 64 kbytes as one page, but an in-page branch instruction "JMP" is a short branch instruction, and an out-page branch instruction "PJMP" is long. It is a branch instruction.

[0004]

However, in the conventional method of setting the short branch instruction and the long branch instruction, it is difficult to set both the short branch instruction and the long branch instruction for all branch instructions such as conditional branch instructions. Met.

For example, in an 8-bit microcomputer, the maximum number of instructions that can be expressed by one word of operation code is 256 words.
Conditional branch instruction, relative branch instruction, or subroutine
Providing short branch instructions and long branch instructions for all branch instructions such as call instructions means that the number of multi-word instructions increases. In this case, the circuit scale of the instruction decoder section increases and the cost of the microcomputer increases. Therefore, conventionally, both short branch instructions and long branch instructions are set only for frequently used instructions, and only short branch instructions are set for conditional branch instructions and long branch instructions are not set. Therefore, the programmer is required to perform programming in consideration of the page structure when creating the program, which causes the productivity of the program to deteriorate. Therefore, in order to solve such a conventional problem, an object of the present invention is to provide a means for preparing a short branch instruction and a long branch instruction for all branch instructions at low cost. Further, another object of the present invention is to obtain an inexpensive and highly functional electronic device by using the semiconductor computing device of the present invention.

[0006]

In order to solve the above-mentioned problems, a semiconductor computer according to the present invention comprises: (1) a) a program instruction storage means for storing a program instruction; and b) an output from the instruction storage means. An instruction storage unit having means for temporarily storing a program instruction to be stored, c) an instruction decoder for decoding the program instruction temporarily stored in the instruction storage unit to generate various control signals, and d) output from the instruction decoder. First address storage means having means for writing data according to a control signal and having means for designating a lower part of an address of the program instruction storage means; and e) an address designated by the first address storage means. Second address storage means for designating an upper part of an address of the program instruction storage means different from each other; f) the instruction decoration A semiconductor computing device comprising address temporary storage means having means for writing data in accordance with a control signal output from the controller, g) the semiconductor computing device includes a branch instruction for branching a program, and h) a branch instruction. Is executed after the first address storage means specifies a part of the address of the program instruction storage means and the data stored in the address temporary storage means is transferred to the second address storage means. , The second address storage means is performed by designating another part of the program instruction storage means.

Alternatively, (2) a) in the semiconductor computing device of (1), data storing means for temporarily storing data, and b) stored in the data storing means in accordance with a control signal output from the instruction decoder. Arithmetic logic operation circuit having means for performing at least addition, logical sum, and logical product of the data, c) a zero flag set to a constant value when the operation result of the logical operation circuit is zero, and the logical operation circuit Has at least one of the carry set to a constant value when the carry result of the operation is carried, and d) a conditional branch instruction that causes a program branch or does not branch depending on the state of the zero flag or carry flag. And e) when the program does not branch at the time of executing the conditional branch instruction, the second address is stored in the address temporary storage means. Wherein the address data stored in the address storage means is written.

Alternatively, the electronic equipment of the present invention is characterized by including the semiconductor computing device of (1), (2) or (3).

[0009]

As described above, by setting the address temporary storage means, it becomes possible to cause all branch instructions to perform long branch and short branch operations. This is because the data is written in the address temporary storage means before the branch execution, and when the branch instruction is executed, the operand data is written in the first address storage means for the lower address and the second address storage means which is the upper address. This is because the data from the address temporary storage means is written. Therefore, all the short branch instructions can fulfill the function of the long branch instruction only by adding one instruction for writing data to the address temporary storage means.

[0010]

1 is a block diagram of a semiconductor computer according to the present invention.

Reference numeral 1 is a program ROM in which program instructions are stored. The program instruction stored in the program ROM is transferred to the data bus 17 in the fetch cycle.
The program instruction written in the instruction register 2 through the instruction register 3 is decoded by the instruction decoder 3 and the micro instruction 16 which is various control signals is output.

The program ROM is a page designation register 4
Are addressed by the program counter 5. When the branch instruction is executed, the operand data, that is, the lower address of the branch destination address is written to the program counter via the data bus, and at the same time, the new page register 6
The upper address data of is written into the page designation register to realize the address designation of the branch destination program instruction. The new page register can write the operand data written in the program ROM via the data bus according to a program instruction.

Reference numeral 10 in FIG. 1 is an ALU (Arithmet).
ic Logic Unit: arithmetic logic operation unit)
That is, arithmetic logical operations such as addition, subtraction, logical product, and logical sum of the data in the temporary register A of 8 and the data of the temporary register B of 9 are performed. Temporary register A and temporary register B have data RAM according to the micro instruction.
The data stored in 7 can be written via the data bus. In addition, the calculation result of the ALU is written in the reminder register C, and is transferred to the data RAM via the data bus.
It can also be returned to.

When the operation result of the ALU is "0", the zero flag register 13 is set to "1", and when it is not "0", it is reset to "0". When a carry signal is generated in the addition result of the ALU, the carry flag register 12 is set to "1", and otherwise it is reset to "0". The zero flag signal 14 and the carry flag signal 15 are control signals for branch judgment of conditional branch instructions in the instruction decoder.

A specific program example is shown below.

PSET next_page JMP C, next_step “PSET next_page” is an instruction to write the branch destination page, next_page, to the new page register.

"JMP C, next_step" is a conditional branch instruction for writing the lower address of the branch destination, next_step, when the carry flag is set in the program counter.

When the condition is satisfied, that is, when the carry flag is set, "JMP C, next_s
When "tep" is executed, "next_step" is written in the program counter, and at the same time, "next_page" stored in the new page register is written in the page register to realize an out-of-page branch.

When the condition is not satisfied, that is, when the carry flag is reset, "JMP C, ne
When "xt_step" is executed, "next_step" is not written to the program counter and is incremented, and at this time, the data stored in the page designating register which is the current page is written back to the new page register.

Therefore, the processing of the current page can be continued without being aware of the branch destination page.

[0021]

As described above, the present invention enables a long branch, that is, an out-of-page branch for all branch instructions by adding a small-scale circuit called a new page register. Also, of course, in the case of branching within a page, "PSET"
It does not slow down the execution speed or lengthen the program length because it is not necessary to insert the instruction before the branch instruction.

As described above, according to the present invention, it is possible to realize a microcomputer which enables a program with low cost and a high degree of freedom.

By using the semiconductor computing device of the present invention, it is possible to use almost common module programs from small-scale programs to large-scale programs, which is particularly effective when developing various electronic devices. Therefore, an electronic device using the semiconductor computing device of the present invention is also included in the present invention.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor computer according to the present invention.

[Explanation of symbols]

 1 ... Program ROM 2 ... Instruction register 3 ... Instruction decoder 4 ... Page designation register 5 ... Program counter 6 ... New page register 7 ... Data RAM 8 ... Temporary register A 9 ... Temporary register B 10 ... ALU 11 ... Temporary register C 12 ... Carry flag register 13 ... Zero flag register 14 ... Carry flag signal 15 ... Zero flag signal 16 ... Micro instruction 17 ・ ・ ・ Data bus

Claims (3)

[Claims] 1. A) program instruction storage means for storing program instructions; b) instruction storage means having means for temporarily storing program instructions output from the instruction storage means; and c) temporary storage in the instruction storage means. An instruction decoder for decoding the generated program instruction to generate various control signals; and d) means for writing data in accordance with the control signal output from the instruction decoder, and the lower part of the address of the program instruction storage means First address storage means having means for designating; e) second address storage means for designating an upper part of the address of the program instruction storage means different from the address designated by the first address storage means; f) Address having means for writing data according to the control signal output from the instruction decoder G) the semiconductor computing device includes a branch instruction for branching a program, and h) the execution of the branch instruction is performed by the first address storing means by the program instruction storage. A part of the address of the means is designated, and after the data stored in the address temporary storage means is transferred to the second address storage means, the second address storage means is replaced by the other program instruction storage means. A semiconductor computing device characterized by being performed by designating a part of. 2. A semiconductor computer according to claim 1, wherein the data storage means temporarily stores data, and b) the data stored in the data storage means according to a control signal output from the instruction decoder. An arithmetic logic operation circuit having means for performing at least addition, logical sum, and logical product of c), c) a zero flag which is set to a constant value when the operation result of the logic operation circuit is zero, and the operation of the logic operation circuit It has at least one of the carry set to a constant value when the result is carried, and d) it has a conditional branch instruction that causes a program branch or does not branch depending on the state of the zero flag or carry flag. E) If no program branch occurs during execution of the conditional branch instruction, the second address is stored in the address temporary storage means. 2. The semiconductor computer according to claim 1, wherein the address data stored in the memory is written. 3. An electronic apparatus including the semiconductor computer according to claim 1 or 2.