JPH011978A - Inspection equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC testing technique and a technique that is particularly effective when applied to testing the electrical characteristics of an IC memory.
The present invention relates to a technique effective for use in a tester for classifying C memories according to their performance.

[Prior Art] Semiconductor devices such as IC memories have electrical characteristics that vary due to variations in the manufacturing process.

Therefore, they are classified into high-speed, medium-speed, and low-speed quantities according to their electrical characteristics, that is, the operating speed. This classification of products involves putting the signal output from a semiconductor device into a tester.

This was done by determining the output waveform at appropriate timing.

As shown in FIG. 5, the conventional tester 10 includes a comparator 11, a timing generation circuit 12 that provides judgment timing, and a comparison voltage generation circuit 13 that provides a high-side comparison level VOH and a low-side comparison level VOL. The configuration was common.

[Problems to be solved by the invention] Conventional testers have only one comparator, so the output waveform of one semiconductor device can only be judged at one point (timing). . Therefore, when classifying products, the judgment timing for one semiconductor device is changed and three tests are performed: a high-speed product test, a medium-speed product test, and a low-speed product test, as shown in Figure 7. It was necessary to conduct a test. Therefore, the conventional tester has a problem in that it takes a long time to test one semiconductor device.

An object of the present invention is to provide a tester that can test ICs for product classification according to electrical characteristics in a short time.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, the IC tester is provided with a plurality of comparators, and is also provided with a comparison voltage generation circuit that supplies different comparison voltages to each comparator, or a timing generation circuit that provides mutually different comparison timings.

[Operation] According to the above-described means, it is possible to compare one output waveform with different comparison voltages and make a decision using a plurality of comparators, or to make a decision by comparing it with one comparison voltage at different timings, thereby, By making it possible to perform a test for product classification according to electrical characteristics by determining the output waveform once, it is possible to achieve the above object of shortening the test time for semiconductor devices.

Embodiment FIG. 1 shows a first embodiment of a memory tester to which the present invention is applied.

In this embodiment, three comparators lla, llb, and llc are provided in one tester 1o, and common comparison levels VOH and VOL are applied from a comparison voltage generation circuit 13 to each of the comparators lla to 11C. Also,
Each comparator 11a.

Timing generation circuits 12a and 12b provide different determination timings corresponding to signals 11b and llc.

12c is provided. And each comparator
One signal output from the output pin 21 of the semiconductor device 20 is commonly input to the input terminals of a to llc,
The configuration is such that one output waveform can be judged in parallel using three comparators.

In the tester of this embodiment, first, the timing generation circuit 12a supplies the determination timing signal STBa to the comparator lla, and then, after a short delay, the second Judgment timing signal 5T from timing generation circuit 12b
Bb is supplied to the comparator 11b, and a little later than that, the third timing generation circuit 12b supplies the determination timing signal S T B c to the comparator llc.

Judgments are made at different timings. Further, the comparison voltage generation circuit 13 outputs a level “1” or “0” of the signal output from the semiconductor device 20.
” (known in advance to the tester), the high-side comparison level VOH or the low-side comparison level VOL is applied to each of the comparators lla to llc before the determination timing signal 5TBa is supplied. It has become.

According to this embodiment, as shown in FIG. 3, for one output waveform, three different timings 5TBa, 5T
A determination will be made based on Bb and 5TBc. Therefore,
As shown in FIG. 6, high-speed products, medium-speed products, low-speed products, and defective products can be determined by one test. In other words, in FIG. 3 showing the output waveform, at timing 5VBa, the output level "1" is already higher than VOH and the output level "O" is Voc, and if it is lower, it is determined that it is a high-speed product, and at timing S T B a, the above conditions are met. However, timing 5TBb is considered a medium-speed product when the above conditions are met, and timing S T B a and 5T.
' does not satisfy the condition in Bb, but the timing S T B
In c, a rower that satisfies the conditions can be determined to be a low-speed product. Furthermore, if the output level does not reach Voo or VOL even at timing S T B c, it can be determined that the product is defective, and this determination can be made in one test.

FIG. 2 shows a second embodiment of the memory tester according to the present invention.

In this embodiment, similarly to the first embodiment, three comparators lla, 11b, and lie and timing generation circuits 12a, 12b, and 12c that provide different judgment timings to these comparators are provided in the memory tester 10. ing. Furthermore, in this embodiment, a comparison voltage generation circuit 1 is provided which provides different comparison levels V o o and VOL to the comparators lla, 11b, and lie.
3a.

13b and 13c are provided. in particular.

The first comparison voltage generation circuit 13a generates the highest high side comparison level V OHa among the three for the comparator 11a.
Or the lowest low side comparison level V.

La, and the third comparison voltage generation circuit 1'3c
The lowest high-side comparison level V OHc or the highest low-side comparison level V OL c among the three is applied to the comparator llc. Then, the second comparison level generation circuit 13b generates a high-side comparison level V OHb between the comparison levels ■OHa and vOHC, and a low-side comparison level V OL between VOL a and VOLQ, for the comparator llb. It is designed to give b. In other words, compared to the high side, Be/L/VOHa, Vo o
b, Vooc have the relationship Vooa>Voub>Vooc, and the low side comparison levels VOLa, V
OL b, V OL Q is vOLakuV o L
The relationship is b < V OL c.

In the tester of this embodiment, comparators lla,
The same judgment timing signal S for llb and llc
T B a , S T B b , S T B c
are applied from the comparison voltage generation circuits 13a, l3b, and 13c, as shown in FIG. 4, judgments are simultaneously performed on one output waveform using three different comparison levels on the high side and the low side. be done.

Then, at this judgment timing, the output level “1” becomes V
'ooa, and the output level "0" is VOL a
If it is lower than (first condition), it is determined to be a high speed amount, and the output level "1" is lower than V o Ha but higher than V OHb, and the output level "0" is higher than VOLa but V OL
If it is lower than V o Hb (second condition), it is determined to be a medium-speed product, and furthermore, although the output level "1" is lower than V o Hb, V O
If it is higher than Hc and the output level "O" is higher than voLb but lower than V OL c (third condition), it can be determined that it is a low-speed product. Also, the output level “1” is V
If the output level "0" is lower than OHc or higher than VOLc, it can be determined that the product is defective, and this determination can be made in a single test as shown in FIG.

Moreover, if the tester of this second embodiment is used.

The same comparison levels V, o H, Vo L are applied to the comparators lla, llb, llc from each comparison voltage generation circuit 13a, 13b, 13c, and the same comparison level V, o H, Vo L is applied to the comparators lla, llc from the timing generation circuits 12a, 12b, 12c.
Judgment timing signals 5TBa and '5TBb are different from each other for lb and lie.

By applying 5 TBc, it is possible to perform the same determination as in the tester of the first embodiment, that is, the determination of the output waveform as shown in FIG.

Furthermore, if the tester of this second embodiment is used.

By making the determination timing and comparison level different for each comparator, it is possible to test an IC memory in which the output takes three levels instead of the binary values of "0" and "1".

In the above embodiment, one tester is provided with three comparators.

The present invention is not limited thereto, and two or four or more may be provided. Furthermore, in the above embodiments, there is one in which a timing generation circuit and a comparison voltage generation circuit are provided for each of the three comparators (second embodiment), and one in which only a timing generation circuit is provided for each comparator on a one-to-one basis. In the first embodiment, the comparison voltage generation circuit is made to correspond to each comparator on a one-to-one basis, and a common timing generation circuit is used. It can also be configured.

As explained above, in the above embodiment, a memory tester is provided with a plurality of comparators and a comparison voltage generation circuit that supplies different comparison voltages to each comparator or a timing generation circuit that provides mutually different comparison timings. Therefore, one output waveform can be judged by comparing it with different comparison voltages using multiple comparators, or it can be judged by comparing it with another comparison voltage at different timings. It has become possible to perform tests for product classification according to electrical characteristics4.This has the effect of shortening the test time for semiconductor devices6. Although the present invention has been specifically described based on the above embodiments, it goes without saying that the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the spirit thereof. For example, in the above embodiment, the timing generation circuit that provides different judgment timings and the comparison voltage generation circuit that provides different comparison levels are shown as separate blocks, but they may be used as long as their functions are the same as those of the embodiment. , combine this into one block (circuit)
It can be shown as

In the above description, the invention made by the present inventor was mainly applied to an IC memory testing device, which is the background field of application, but the invention is not limited thereto.

The present invention can be generally used in testing devices for output signals of logic LSIs and other digital circuits.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, a test for product classification according to electrical characteristics can be performed by determining the output waveform once, and thereby the test time for semiconductor devices can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of an IC tester according to the present invention, FIG. 2 is a block diagram showing a second embodiment of an IC tester according to the present invention, and FIG. 3 is a block diagram showing a first embodiment of an IC tester according to the present invention. FIG. 3 is an output waveform diagram showing a method for determining the output of an IC by the tester of the embodiment. FIG. 4 is an output waveform diagram showing a method for determining the IC output by the tester of the second embodiment. FIG. 5 is a block diagram showing a configuration example of a conventional IC tester, FIG. 6 is a flowchart showing a determination method by an IC tester according to the present invention, and FIG. 7 is a flowchart showing a determination method by a conventional IC tester. 10... Tester, Lla, llb, 11c... Comparator, 12, 12a, 12b, L2c... Timing generation circuit, 13.13a, 13b, 13c...
... Comparison voltage generation circuit, 20 ... IC to be tested (semiconductor device). Figure 1 Figure 2 Figure 3 Figure 4 Figure T5L

Claims (1)

[Claims] 1. A plurality of comparators to which the same output waveform is input, and a timing generation circuit that provides different judgment timings or a comparison voltage generation circuit that provides different comparison levels to these comparators. An inspection device comprising: 2. A plurality of comparators to which the same output waveform is input, a timing generation circuit that provides different judgment timings to these comparators, and a comparison voltage generation circuit that provides different comparison levels. An inspection device according to claim 1, characterized in that: 3. The inspection device according to claim 1 or 2, wherein three of the plurality of comparators are provided.