JPH01199280A - Sequential mask arithmetic processing system - Google Patents

Abstract

PURPOSE:To shorten the processing time of the title system by using a pipeline free from the overlapping processes to perform a mask arithmetic process after fetching once the picture data to a pipeline mechanism in accordance with the mask size. CONSTITUTION:A picture processor performs a mask arithmetic process with use of a mask of (nXm) picture elements (n, m: positive integers). In this case, the picture data is read into a memory functions LM0-2 of a pipeline structure. Then the data necessary for the mask arithmetic process are successively taken out of a reading line memory LM3. Thus the useless multiple fetching actions can be avoided for the picture data given from a main storage MS.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art and Problems to be Solved by the Invention Means for Solving the Problems Actions Examples Effects of the Invention [Summary] n pixels x m pixels ( Regarding the sequential mask calculation processing method in an image processing device that performs mask calculation processing using a mask (n, m are positive integers), the purpose of this is to perform mask processing on image data at high speed, and uses m+1 line memories, After setting the m-bit x n-stage pipeline register and the initial value of the Y-direction address of the image data, the address is updated every time one line of image data is calculated, and the start address ( Y.S.
) and the final address (YE), write the image data to the line memory, read line by line from the line memory to the pipeline register, and write the image data in the mask operation mechanism. A means for controlling peripheral processing in the Y direction and an initial value of the address in the X direction of the image data, and then updating the address for each mask operation for one pixel of image data, and setting the starting address. (XS) and the final address (χE) are detected, and each pixel is read from the line memory to the pipeline register, and the image is
said m.
The image data of m lines read into m lines of the +1 line memory is taken out to the above pipeline register for m pixels, and the read out n pixels × m to the pipeline register are
While sequentially processing mask calculations on the pixel image data using the mask consisting of the above n pixels x m pixels,
The configuration is such that the image data of the next line is transferred to the remaining one line memory.

[Industrial application field]

The present invention relates to a sequential mask arithmetic processing method in an image processing apparatus that performs mask arithmetic processing using a mask of n pixels by m pixels (n+m is a positive integer).

With the recent improvement in the processing power of computer systems and the recent increase in the capacity of memory devices, it has become possible to process images consisting of image data at high speed in fields such as remote sensing (resource exploration, weather exploration, etc.). It's starting to be sought after.

In such image processing, for example, mask calculation processing using a mask consisting of 3 x 3 pixels is often performed, but since the processing speed has traditionally been slow and impractical, it has been difficult to put this mask calculation processing into practical use. There was a need for a mask arithmetic processing method that could process at reasonable speeds.

[Prior art and problems to be solved by the invention] FIG. 3 is a diagram illustrating a conventional mask calculation processing method, and (a)
indicates the relationship between the image expressed as a dot and the pixel, and (
b) shows an example of a 3×3 mask, (c) shows the concept of mask arithmetic processing, and (d) shows an example of the configuration of a conventional mask arithmetic processing device.

Now, dots (pixels) (
Among the mask calculation processing (or also referred to as spatial filter processing) for fi, j), for example, when smoothing processing (smoothing filter processing) is performed using a 3×3 mask as shown in figure (b), gi, J・1/9 (fi-+, j-++fi-to
j+ft-plate, J or 1+ft, j-++f5+J
+'=+i+ft+++ ;-t+f=+++ 4
+ft or I+14+).

In addition, in the differential processing used to find the boundaries of images, etc., gi, j = 1/4 (fi・j-1+fi-1+ a
``'+l+j+f=, J, +-4 ft, J).

In this differentiation process, a negative result may be obtained, but this negative result may be converted into positive data and output.

The mask calculation process described above has the following characteristics.

■ The mask calculation process is local and only applies to adjacent dots (pixels).
It is not affected by the calculation result of .

That is, the calculation result is not returned to the original image.

(This is because the original image data and the mask operation result data are separated, as is clear from figure (d).) ■ The image data is arranged in a two-dimensional manner, which is currently widely used. It is not compatible with the one-dimensional nature of memory, and it takes time to access image data on the memory. (Refer to the data arrangement in main memory device (MS) 20 in the figure (d)) ■ The processing amount of the above mask operation is the square of the image resolution (number of lines, number of pixels per line/unit length) ratio, or the area ratio. Proportional.

In particular, for the reasons of ■ and ■, if this mask operation is executed by an image processing device equipped with a microprocessor (MPtl) 10 shown in FIG.
The microprocessor (MPI) 10 reads the two-dimensional image data arranged in -dimensional representation above.
When performing the above mask calculation processing with the program executed by , as shown in figure (c), when focusing on the pixels (fi,,), the image data in the mask range indicated by 'Ma' is It reads out and performs calculations, and calculates the next adjacent pixel (ft++
, j), it was necessary to read out the image data in the range indicated by Mb' and perform the calculation.

Therefore, as is clear from figure (c), the pixel (fi,
, ) and nine pixels (r=, +, J), it was necessary to repeatedly read the data of the same pixel (indicated by diagonal lines) from the main memory (MS) 20.

In addition, in this method, as described above, the mask operation itself is performed by a program executed by the microprocessor (MPU) 10, so there is a problem in that it takes more processing time.

Other conventional mask calculation processing methods include (d
) In the figure, there is an image processing device equipped with a dedicated mask operation mechanism 5' indicated by a dashed line. ) 20 to the mask calculation mechanism 5
The means for transferring image data to the pixel (f5+j+fi.114.) is not particularly different from the method described above.
When performing - series of mask calculations for each pixel in −・−), the data of the same pixel is processed how many times (
There is a problem in that it is necessary to input the data into the mask calculation mechanism 5' for up to three times.

In this conventional method, for example, an A4 size 2
By processing image data of 40 dots per inch (dpi),
There was a problem in that it required several minutes to several tens of minutes and was impractical.

In view of the above-mentioned drawbacks of the conventional art, the present invention has been developed using n pixels x m pixels (n,
In an image processing device that performs mask arithmetic processing using a mask (m is a positive integer), when capturing image data from the main memory (MS), it stops repeatedly capturing the same pixels and adapts to the size of the mask. The purpose of this invention is to provide a method for performing high-speed mask calculation processing by importing the captured image data into a pipeline mechanism and then processing the captured image data in a pipeline manner.

[Means to solve the problem]

The above-mentioned problems are solved by a sequential mask operation processing method configured as follows.

An image processing device that performs mask arithmetic processing using a mask of n pixels x m pixels (n and m are positive integers) includes m+1 line memories, m bits x n stages of pipeline registers, and image data processing. After setting the initial value of the address in the Y direction,
Every time one line of image data is calculated, the address is updated, and the start address (YS) and end address (Y
E) is detected, the image data is written to the line memory, the line unit is read from the line memory to the pipeline register, and the peripheral part of the image data in the Y direction is detected by the mask calculation mechanism. After setting the initial value of the X-direction address of the image data, the address is updated every time a mask operation is performed on one pixel of image data, and the start address (XS) and the final address are updated. Detecting the address (XE) and reading out each pixel from the in-memory to the pipeline register;
means for controlling the processing of the peripheral part of the image in the X direction in the mask calculation mechanism, and the image data of the m lines read out to the m lines of the m+1 line memories are stored in the pipeline register by m pixels. For the image data of n pixels x m pixels taken out to the pipeline register, mask operations are sequentially processed using the above mask of n pixels x m pixels, and the remaining image data of the next line is processed. The configuration is such that the data is transferred to one line memory.

[Effect]

That is, according to the present invention, in an image processing device that performs mask calculation processing using a mask of n pixels x m pixels (n and m are positive integers), image data is read into a memory mechanism with a pipeline structure, and the corresponding Data necessary for mask calculation processing is sequentially taken out from a pipeline mechanism to stop wasteful multiple loading of image data from a main memory (MS).

■ Pipelining memory access: In other words, a 3 x 3 pixel mask operation requires at least 3 lines of data from an image, so in the present invention, 4 line memories (LMO to 3 ), three of them are used as current, and the remaining one is used as a line memory for reading the next line.

In other words, the 1st to 3rd lines of the image are stored in the line memory (LMO~2).
After reading the image data into the LM, a mask operation is executed, but in parallel with this process, the next 4th row of image data is stored in the line memory (LM
3) Lead to. When the mask operation processing for these three lines is completed, the contents of the line memory (LMO) are no longer needed, so while processing the contents of the line memory (LMI~3), the 5th line is stored in the line memory (LMO). Read image data.

While wrapping around the line memories (LMO to 3) in this manner, mask calculation processing for all images is continued.

■ Pipelining of arithmetic processing of adjacent dots: As a mask arithmetic processing of 3×3 pixels, for example, gi+j・Φ(
f i −1+ j −1+ LAJ, I +mu, Eng.
+, fi-1+ j+L-j・muj-L"-"'◆1
gi+l+j・Φ anal, u, mu, engineering, I + fi + 2 + J -1+ h engineering Lf k + 2 + 'J + also 1. The underlined parts are common in the mask calculation processing shown in (I+fi+2+'j+1).

Therefore, these pixels are stored in the main memory (
Focusing on the fact that there is no need to read pixels from MS) or recalculate masks, the present invention performs pipeline processing without such duplicate processing when processing in the row direction. , performs efficient mask calculation processing.

Therefore, after the image data is adjusted to the size of the mask and imported into the pipeline mechanism, mask calculation processing is executed by means of a pipeline that does not overlap, resulting in a significant reduction in memory access and processing time. This has the effect of significantly reducing the amount.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram illustrating an example of the configuration of a line memory of the present invention, in which (a) shows an example of the configuration; b) is a diagram showing means for transferring image data to the line memory, in which the line memory (LMO~3) 1, the pipeline register (PLRO~2) 3, and the line memory (LMO~3) in FIG. ~3) 1 and the pipeline register (PL
The access mechanism 2.4 to RO~2)3 is the means necessary to implement the invention. Note that the same reference numerals indicate the same objects throughout the figures.

The sequential mask calculation processing method of the present invention will be explained below with reference to FIGS. 1 and 2.

In this embodiment, a case where mask calculation processing is performed using a 3×3 pixel mask will be explained as an example, but it goes without saying that in general, mask calculation processing consisting of n×m pixels may also be used. It is.

First, the initial WA value (
For example, if you set 0°), CS control, MPX
The control unit 24 is energized and the first line memory (LMO)
At the same time, the YS detecting section 22 detects that the contents of the X address register (Y-adr) 21 are the initial values, and instructs the mask calculation mechanism 5 to perform peripheral processing in the Y direction, thereby processing the image data. When an initial value (for example, all "0") is set to the X address register (X-adr) 11 that specifies the in-row address of each line of the Synchronously, the image data of the first line is transferred from the main memory (MS) (not shown) to the line memory (LMO) 1, and when the data transfer of the one line is completed, the X address register (Ladr) is transferred. Updated (+1) in 21
The operation is performed, energizing the CS control and MPX control unit 24, and instructing the second line memory (LMI) 1 to transfer data from the main memory (MS) by the same transfer operation as above. The image data of the second line is transferred to the line memory (LMI) 1.

When such an initial transfer operation is completed, when the initial value is set again in the X address register (X-adr) 11, the XS detection unit 12 sets the X address register (X-adr)
-adr) 11 is an initial value, and instructs the mask calculation mechanism 5 to perform peripheral processing in the X direction.

Thereafter, in synchronization with the update (+1) operation of the X address register (X-adr) 11 from the line memory (LMo, 1) 1, based on instructions from the CS control and MPX control unit 24, the line memory (LMo, 1) Image data addressed to one pixel from 1 is transferred to the right two of the pipeline registers (PLRO to 2) 3 via the multiplexer (MPX) 17 and sequentially shifted.

In the mask operation mechanism 5, for example, the contents of the leftmost register of the pipeline register (PLRO~2) 3 are all While considering it as 0゛,
Based on the peripheral processing instruction from the XS detection unit 12, the beginning of the pipeline register (PLRO~2) 3 is regarded as, for example, all °O'', and the above-mentioned Mask calculation processing is executed.

In parallel with this mask calculation process, the X address register (X
-adr) 11, X address register (Y-adr) 21 is CS controlled, MP
The third line of image data instructed via the X control unit 24 is transferred from the main memory (MS) to the line memory (LM3) 1
will be forwarded to.

Therefore, when the mask calculation process for the first line is completed, the next line memory (
LMO~2) The contents of 1 are multiplexer (MPX) 1
One pixel is transferred from each line to the pipeline register (PLRO~2) 3 via #, and the beginning of the pipeline register (PLRO~2) 3 is transferred based on the instruction from the XS detection unit 12. After the peripheral processing described above is performed, the mask calculation processing described above is executed.

In parallel with this mask calculation process, the X address register (X
-adr) 11 update (+1) operation core, X address register (Y-adr) 21 is CS control, MP
The image data of the fourth line instructed via the χ control unit 24 is transferred from the main memory (MS) to the line memory (LM3) 1
will be forwarded to.

Therefore, the mask operation processing for the next second line is executed by transferring the contents of the line memory (LMI-3) 1 to the pipeline register (PLRO-2) 3.

The relationship between the above image data and the line memory (LMO~3) 1 is as shown in Figure 2, where the Y address (line address) is processed by modulo 4 (that is, divided by "4"). The line memory (LM
O~3) address, C3 control, MPX control unit 2
4, the in-memory (LMO~3) 1 is selected from the main memory (MS).

Specifically, the selection operation in the multiplexer (MPX) 11 is controlled to select three line memories by allowing circulation from four line memories. That is, line memory LMo, 1→LM0.1.2 =>LMI
.

2+3 =>LM2+3+0 =OLMVO+1+=+
3×3 pixels are sequentially transferred to the pipeline (PLRO to 2) while selecting the line memory (L to 3) in a rough round-the-clock manner, such as LMO+1+2 =O-.

In the above operation, the X address register (X-adr
) 11 detects the final address (XE) in the XE detection unit 1
3 is detected, the mask operation mechanism 5 is instructed to perform peripheral processing for the final pixel, and then the next line is processed. At this time, first, the Y address register (Y-adr) is
21 is updated (+1), and as mentioned above, the selection of the line memory (LMO~3) 1 to be read next and the pipeline register (PL) at the multiplexer (MPX) 11 are performed.
RO~2) Selection control for 3 is CS control, MP
This is performed by the X control unit 24, and the X address register (X
-adr) 1.1 is set to the initial value.

In this manner, the vE detection unit 23 operates on the last line, detects the last line, and instructs the mask calculation mechanism 5 to perform peripheral processing on the last line.

In the above embodiment, the X address register (X-
adr) 11. Y address register (Y-adr)
Although the update processing of No. 21 has been described as °+1゛, it goes without saying that it is not limited to this.

At this time, the amount of image data shift operation in the pipeline register (PLRO~2) 3 will differ depending on the update step.
O~3) 1 to 8 pipeline registers (PLRO)
~2) Multiplexer (MPX) when reading to 3
The selection operation at step 11 will be different.

As described above, the present invention provides an image processing apparatus that performs mask calculation processing using a mask of n pixels x m pixels (n and m are positive integers), for example, when performing mask calculation of 3 x 3 pixels, Four line memories and a pipeline register of 3 rows x 3 stages are provided, and the data of each line from the image data is read into the line memory, for example, for 3 lines, and the data of the above 3 rows x 3 stages is sent to one pixel. It is read while being shifted to the pipeline register, and while performing mask operation processing in the mask operation mechanism, based on the address indicated by the row direction address register at that time (specifically, the address in the row direction is processed using modulo 4). The image data of the next line is read into the next position of the line memory (with the representative value as the address), and the same pixel is stored in the main memory
) The feature is that mask operations are performed sequentially in a pipeline format without repeatedly reading the image data above.

〔Effect of the invention〕

As explained above in detail, the sequential mask operation processing method of the present invention is implemented in an image processing apparatus that performs mask operation processing using a mask of n pixels x m pixels (n and m are positive integers). After setting the initial values of the line memory, the m-bit x n-stage pipeline register, and the address of the image data in the X direction, the address is updated every time one line of image data is calculated, and Start address (Y
S) and the final address (YE), write image data to the line memory, read line by line from the line memory to the pipeline register, and read the image data in the mask operation mechanism. after setting an initial value of an address in the X direction of the image data, updating the address for each mask operation for one pixel of image data, and starting the Means for detecting an address (XS) and a final address (XE) and controlling reading of each pixel from the line memory to the pipeline register and processing of the peripheral part of the image in the X direction in the mask calculation mechanism. The image data of m lines read into m lines of the m+1 line memory is taken out for m pixels to the pipeline register, and the read n pixels x
For m-pixel image data, the mask operation is sequentially processed using the above-mentioned mask consisting of n pixels x m pixels, and the image data of the next line is transferred to the remaining one line memory. Therefore, after inputting the image data to the pipeline mechanism according to the size of the mask, mask calculation processing is executed by means of a pipeline that does not overlap, significantly reducing memory access and processing time. There is an effect that mask calculation processing can be performed on image data at high speed, which can achieve a significant reduction.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a diagram illustrating an example of the configuration of a line memory according to the present invention. FIG. 3 is a diagram illustrating a conventional mask calculation processing method. It is. In the drawing, 1 is a line memory (LMO~3). One is a multiplexer (MPX). 2.4 is an access mechanism for the line memory (LMO~3), pipeline register (PLRO~2), and mask operation mechanism. 11 is an X address register (X-adr). 12 is an XS detection section, and 13 is an XE detection section. 21 is Y address register (Y-adr) + 22 is YS
Detection unit 23 is a YE detection unit. 24 is a CS control and MPX control section. 3 is a pipeline register (PLRO~2). 5.5゛ is a mask calculation mechanism. fi+j+ ・- is each dot (pixel) of image data. 10 is a microprocessor (MPU). 20 is a main memory (MS). are shown respectively. Agent Patent attorney Igeta Sada - Transfer・'Pa':...,','),, 1 \te2 (α) (shi) Introduction\Shape of the Moon // Seven Rimesomizoji〈・( ri'] Beggar's illusion is night 2] 乎 2 口 (a) ('b) い 禮米のmass million! 's square million East'~
Pole 30 (Dono 2)

Claims (1)

[Claims] An image processing device that performs mask arithmetic processing using a mask of n pixels x m pixels (n and m are positive integers), comprising: m+1 line memory (1) and m bits x n stages. After setting the initial values of the pipeline register (3) and the Y-direction address of the image data,
Each time one line of image data is calculated, the address is updated, and the start address (YS) and end address (Y
E), writing image data to the line memory (1) and reading line by line from the line memory (1) to the pipeline register (3);
Furthermore, means (2) for controlling the processing of the peripheral part of the image data in the Y direction in the mask calculation mechanism (5), and after setting the initial value of the address in the X direction of the image data, the image data of one pixel is set. The address is updated every time a mask operation is performed, and the start address (XS) and final address (XE) are detected, and each pixel is read from the line memory (1) to the pipeline register (3). and a means (4) for controlling the processing of the peripheral part of the image in the X direction in the mask calculation mechanism (5), so that the m lines read out in the m lines of the m+1 line memory (1) are provided. Transfer the image data to the above pipeline register (
3), extract m pixels and store the corresponding pipeline register (3).
) Regarding the image data of n pixels x m pixels taken out,
A sequential mask operation characterized in that the image data of the next line is transferred to the remaining one line memory (1) while sequentially processing the mask operation using the above-mentioned mask consisting of n pixels x m pixels. Processing method.