JPH01199465A - semiconductor storage device - Google Patents

Abstract

PURPOSE:To enable a transistor to be equipped with an adequate capacitor capacity and to allow an open bit line system and a folded bit line system to be constituted to occupy a relatively small area by a method wherein memory cells connected to neighboring bit lines are designed to use a common transfer gate. CONSTITUTION:In a separated-and-merged type semiconductor storage device wherein one transistor cell Mb is provided with one bit line contact window 10b and one capacitor region 5 is provided on the outer circumference of a field island 15, a pair of transistor cells Mb and Md respectively connected to neighboring bit lines are connected to one work line 11 neighboring with each other through a transfer gate 13, and their respective bit line contact windows 10b and 10d in a plan view are provided in a zigzag through the intermediary of the word line 11. Further, a capacitor region 5a for the transistor cell Mb, out of the pair of transistor cells Mb and Md is allowed to extend as far as the side of a field island 15 of the other transistor cell Md through the intermediary of a insulating film 8.

Description

Detailed Description of the Invention (Summary) Regarding a separate/combined semiconductor memory device having a capacitor region on the outer periphery of the field island between adjacent field islands whose elements are isolated, the capacitor region for one transistor is The purpose of this is to obtain a sufficient capacitor capacity by dividing the bit lines, and to be able to configure both the oven bit line method and the folded pit line method in a relatively small area. A pair of transistor cells are connected side by side to one word line with a common transformer 77 gate, and respective bit line contact windows are provided in a staggered manner via the word line in a plan view, and further,
The capacitor region for one of a pair of transistor cells is extended to the side of the field island of the other transistor cell via an insulating film.

[Industrial application field]

The present invention relates to a separation/merging type semiconductor inter-semiconductor TM device having 11 main passator regions around the outer periphery of a field island between adjacent field islands whose elements are isolated.

For example, in a dynamic RAM (DRAM) or the like, 1-setting is performed by a transfer gate transistor connected to the intersection of a bit line and a word line. In this case, a semiconductor memory device having the above configuration is used as the transfer gate transistor, but this includes one bit line contact window (N window) and one capacitor region for one transistor. The so-called N-window one-cell type, which is
There is a so-called N-window 2-cell type that has one window and two capacitor regions. The present invention is applied to this back N window 1 cell type.

On the other hand, in a transistor type memory cell, since the amount of signal that can be taken out to the bit line during reading is relatively small, a sense amplifier is required to detect and amplify this signal. There are two types of layout methods for connecting memory cells to bit lines and word lines connected to the sense amplifier: an open bit line method and a folded bit line method. The front tone has a configuration in which memory cells connected to adjacent word lines are connected to one of two bit lines sandwiching a sense amplifier; It has a configuration in which it is connected across two bit lines with a sense amplifier in between.

Here, for example, when configuring the N-window 1-cell type semiconductor memory device, a sufficient capacitor capacity can be obtained, and moreover,
In both the open bit line method and the folded bit line method, it is desirable to be able to configure the device in a relatively small area.

[Conventional technology]

FIG. 3 shows plan views of six examples of conventional open bit line type devices. 501 in (A) and (B) of the same figure.

502.503.504 LtN window 1 cell type Nodoranshu? Each gate transistor has one N window (511~
514), there is one capacitor area (521 to 52).
4) Provided. 53 is a transfer gate (word line). This has a configuration in which memory cells (for example, 50+, 503) connected to adjacent word lines 53 are connected to one of two bit lines (indicated by a broken line) with a sense amplifier (not shown) in between. Eggplant.

Generally, in a DRAM etc., as shown in FIG. 3, 1-input is performed by a transfer gate transistor ``[r'' connected to the intersection of a bit line and a word line.

FIG. 4 shows a plan view of an example of a conventional 4A folded bit line system. In the same figure, 54+, 542.

43.544 is an N window 1 cell type transfer gate.
One capacitor region (561 to 564) is provided for each N11 transistor (551 to 554). 57 is a word line. In this case, memory cells (for example, 542 and 54+, 544 and 543) connected to adjacent word lines 57 straddle two bit lines (indicated by broken lines) with a sense amplifier (not shown) in between. Make a connected configuration.

In both Figures 3 and 4, the cell area is the bit line pitch (
B) and the word line bit (W) (represented by B
．． 75μ■2, and b shown in FIG. 4 is 5μ■×2.
5 μ = 12.571 plow 2.

[Problem that the invention seeks to solve]

The conventional device can be configured with a relatively small area (8.75 μm2) in the open bit line system shown in FIG. 3, but can be constructed in a relatively large area (12.5 μm2) in the folded bit line system shown in FIG. There was a problem. On the other hand, in the conventional device, since each memory cell is configured independently, there is a limit to the size of the capacitor area even if one tries to take the capacitor capacity ω, and there is a problem that it is not possible to take a sufficient capacitor capacity. There was a point.

According to the present invention, a sufficient capacitor capacity can be obtained by increasing the capacitor capacity for one transistor, and
It is an object of the present invention to provide a 'f=conductor memory device that can be configured in both an open bit line type and a folded bit line type in a relatively small area.

(Means for Solving Problem No. 171) The present invention provides an N-window one-cell type transfer gate transistor in which one bit line is connected to each adjacent bit line.
Pairs of transistor cells are connected side by side to one word line with a common transfer gate, and respective bit line contact windows are provided in a staggered manner via the word line in a plan view, and The capacitor region for one of the transistor cells is extended to the side of the field island of the other transistor cell via an insulating film.

[Effect]

Memory cells connected to adjacent bit lines share a common transformer 7? Since the N window is configured using a transfer gate, when applied to a folded bit line method, both the pitch and word line pitch are smaller than those of conventional devices. Can be configured in a short manner. Further, since the capacitor region in one transistor cell is formed to extend to the side of the adjacent transistor cell via the insulating film, a sufficient capacitance can be obtained for one transistor cell.

〔Example〕

FIG. 1 is a plan view of one embodiment of the present invention 5Aδ, and FIG. 2 (A
) is A-AI! in Figure 1. Sectional view along it, Fig. 2 (
B) is a sectional view taken along line C-C in Figure 1, Figure 2 (C)
1 respectively show cross-sectional views taken along the line CC in FIG. 1.

In FIGS. 1 and 2, reference numeral 1 denotes shallow trench isolation, which is provided on the substrate 2. 3 is a cell plate, 4 is a capacitor insulating film, 15 is a field island, 5 is a capacitor storage electrode, 6 is an oxide film, and 7 is a channel cut impurity layer.

Further, 8 is a living room insulating film, and 9 is a source or drain impurity diffusion layer.

Here, in FIG. 1 and FIG. 2(C), 10a is a bit line contact window (N window) of a certain memory cell Ma, and 10b is a memory cell adjacent in the longitudinal direction of the word line 11 via the cell plate 3. It is an N window of Mb. Also, in Figure 1, 1
0c and 10d are N windows of memory cells MC and Md adjacent in the longitudinal direction of bit lines 12 (FIG. 2<8) and (C) of memory cells 1vla and Mb, respectively. Reference numeral 13 denotes a transfer gate, which connects adjacent memory cells (for example, Mb).

Md) and is connected to the word line 11 via the word line contact window 14. In the present invention, adjacent memory cells (for example, Mb, Md) are configured using a common transfer gate 13,
The N window (10b.

10d) is formed by sandwiching the transfer gate 13. The same applies to other memory cells.

Incidentally, the capacitor storage electrode 5 extends to the area of adjacent memory cells. That is, in the plan view shown in FIG. 1, for example, the capacitor storage electrode 5a of the memory cell Mb is the adjacent memory cell Md.

The capacitor storage voltage 145d of the memory cell Md is formed by extending through the interlayer insulating film 8 to the Me region.
Similarly, it is formed to extend through the living room insulating film 8 to the area of the adjacent memory cell 5a. Other memory hill capacitor stack electrodes have a similar configuration.

In this way, the capacitor storage electrode of one transistor is formed to extend to the side of the adjacent transistor, so there is sufficient space between the capacitors for one transistor, and a sufficient capacitance can be achieved compared to conventional devices. Obtainable. Further, since the N windows of adjacent transistors are arranged in parallel in a so-called staggered pattern, a sufficient distance can be maintained between the N windows of adjacent transistors, and interference of bit line voltages can be prevented.

Further, the configuration shown in FIG. 1 is a folded bit line system. That is, memory cells (for example, memory cells Mb) connected to adjacent word lines 11.

Mc) is a bit line with two sense amplifiers (N window is 10b,
10c). In this case, adjacent memory cells (for example, Mb, Md) are configured using a common transformer 77 gate 13, and the N
Since the windows (10b, 10d) are formed sandwiching the transfer gate 13, the bit line pitch is set to 1.9, for example.
μm1 word line pitch can be configured smaller than the conventional device, for example, 1.4 μm, and the cell area is 1.9 μl x 1.4 μm.
m=2.66μ12, making it relatively smaller than the conventional device shown in Figure 7P44.

On the other hand, it can also be applied to an open bit line system in this state. That is, the configuration is such that adjacent memory cells Md and Me are connected to one of two bit lines sandwiching a sense amplifier. .

Therefore, in the present invention, both the folded bit line system and the open bit line system can be configured in a relatively small area, and in particular, the folded bit line system can be configured smaller than in the conventional example.

〔Effect of the invention〕

As explained above, according to the present invention, memory cells connected to adjacent bit lines are configured using a common transfer gate, and the N window is configured to sandwich the transfer gates, so that a fall occurs. When applied to the dead bit line method, both the pit line pitch and the word line pitch can be made 90 times smaller than in conventional devices, and the capacitor area in one transistor cell is connected to the adjacent transistor cell through an insulating film. Since it is formed to extend to the side, a sufficient capacitor capacity i for one transistor hill can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a plan view of the present invention; Fig. 21i1 is a sectional view taken along lines A-AM, B-B, and C-C in Fig. 1; Fig. 3 is a plan view of each of the open bit line system of the conventional device. FIG. 4 is a plan view of an example of a folded bit line method of a conventional device. In the figure, 1 is a vertical trench isolation, 3 is a cell lead, 4 is a capacitor insulating film, 5.5a and 5b are capacitor storage electrodes (capacitor region), and 10a to 10d are bit line contact windows (N window). , 11
12 is a word line, 12 is a bit line, 13 is a transformer 77 gate, 14 is a word line contact window, 15 is a field island, and M a - M e are transistor cells.゛Special applicant: Fujitsu Co., Ltd. Agent: Patent attorney: Tadahiko Ito ゛Ma
Mc r-1/\-1, 2--/\--1's 0 Kikanshi throat flat (Meshu shout 1: early 1st inning A-A line, B-β#L1: Shunwamu carp 11 Nippon,
Figure 2 (deme 1)

Claims (1)

[Claims] For one transistor cell (Mb), there is one bit line contact window (10b) and one capacitor region (5a) provided at the outer periphery of the field island (15). In a separate/combined semiconductor memory device, a pair of transistor cells (Mb, Md) respectively connected to adjacent bit lines are connected to a single word line (11 ) and the respective bit line contact windows (10b, 10d
) are provided in a staggered manner via the word line (11) in a plan view, and furthermore, a capacitor region (5a) for one transistor cell (Mb) of the pair of transistor cells (Mb, Md) is provided with an insulating film. A semiconductor memory device characterized in that the semiconductor memory device is provided extending to the side of the field island (15) of the other transistor cell (Md) via (8).