JPH01200425A - Power supply controller - Google Patents

Abstract

PURPOSE:To eliminate the influence of the reset pulse produced before the output of a power supply is fixed by invalidating an alarm signal at absence of a power supply application signal and resetting the alarm signal when the power supply is applied again after the fault of the power supply is deleted. CONSTITUTION:An application signal is applied to an AND circuit 15 of a power supply control circuit 14 from a host device as an application/interruption signal 12. Under such conditions, both 1st and 2nd alarm signals 17 and 19 are kept at level '1' and therefore the reapllication of a power supply is impos sible as long as said level '1' is released. Thus, the signal 12 is branched and applied to an alarm resetting signal generating circuit 24. The circuit 24 applies a resetting signal 25 to a latch circuit 20. The circuit 20 resets the signal 19 and gives a 3rd alarm signal 21 of level '0' to the circuit 15. The circuit 15 transmits an application/interruption signal 16 of level '1' to a power supply 11. Thus, the power supply 11 is applied again and its output voltage Vout is boosted. Then an application end signal 26 is sent to the circuit 14 to complete a reapplication action.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a power supply control device used in information processing equipment, etc., and particularly relates to a power supply control device with an improved processing method when an abnormality occurs in the power supply. .

[Conventional technology]

Stabilized power supplies are indispensable in systems using microcomputers, various information processing devices, and ordinary electronic devices, and various systems have been devised and used. On the other hand, even if such a stabilized power supply is used, if the power supply does not operate normally, there is a risk that expensive equipment may be destroyed, so various countermeasures are taken. Among these methods, a method is known in which a power abnormality (hereinafter referred to as an alarm) signal is generated when a power failure occurs, and the power is turned on again after the failure is removed.

FIG. 3 is a block diagram showing a power supply control device that controls power on/off using this type of alarm signal, and FIG.
FIG. 3 is a timing chart showing the operation of this power supply control device.

When an on/off signal 12 is sent to the power source 11 from a host device (not shown), this on/off signal 12 is transmitted to the AND circuit (hereinafter referred to as A) of the power control circuit 14 of the power supply control device 13.
Manually applied to ND circuit>15.

The output of the AND circuit 15 becomes the on/off signal 16, which is further transmitted to the power source 11 as the on/off signal 18 through an OR circuit (hereinafter referred to as an OR circuit) 17. Power supply 1
1 is turned on and off by this. Here, power supply 11
If there is any abnormality, an alarm signal 21 is generated, which is input to the negative input terminal of the AND circuit 15 of the power supply control circuit 14. Since the alarm signal 21 at this time is at logic level 1, a level 0 signal is input to the negative input terminal of the AND circuit 15. Therefore, the input signal 12 from the host device (not shown) is inhibited, and the output signal 16 of the AND circuit 15 has a logic level of 01, and the output signal 18 of the OR circuit 17 also has a logic level of 0. As a result, Hara 11 is disconnected.

Thereafter, a power on/off signal 12 is sent from a host device (not shown) to the power supply control device 13, and when a power on command is issued (a in FIG. 4), the power supply control circuit 14 generates an alarm reset signal for the power supply control device 13. A reset signal generation instruction signal 21 is issued to the circuit 20. This reset signal generation circuit 20
sends a reset signal 22 to an alarm signal latch circuit (not shown) built in the power supply 11 through the OR circuit 17 (b in FIG. 4). As a result, the alarm signal latch circuit (not shown) is reset, and the alarm signal 21 is reset. By resetting the alarm signal 21 in this way (C in Fig. 4), the make/cut signal 1, which had been inhibited at the same time as the alarm signal 21 was generated, is reset.
6 becomes valid again (FIG. 4d). By the way, the reset signal 22 is pulsed on the power-on signal line,
That is, since it is applied to the OR circuit 17, the closing/cutting signal 18 becomes the closing/cutting signal 18 as shown in FIG. 4e.
The reset signal 22 is superimposed before being applied. Therefore, the output of the power supply 11 is ■. , A are put in an unstable state as shown in FIG. 4(f), then cut, and then put in again.

After this state, the output ■. U7 becomes stable, and at that point the power-on completion signal 25 (g in Figure 4) is sent to the power supply control circuit 14.
and the input is completed.

[Problem to be solved by the invention]

As described above, in the conventional power supply control device, when the power is turned on again after processing the power supply abnormality, a reset signal for canceling the alarm signal is applied in a pulsed manner to the power-on signal line. This creates a problem in that the output voltage of the power supply provides an undesirable pulsed output before reaching a stable output state. This has the disadvantage that it adversely affects the logic device and the like as a load.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a power supply control device that can solve the conventional problems by preventing unnecessary output from occurring before the power output becomes constant when the power is turned on again after an alarm occurs. be.

[Means to solve the problem]

The power control device of the present invention includes a circuit that enables a power abnormality signal while a power-on signal is being applied, and a circuit that enables a power-on signal from a host device, etc. when the power is turned on again after being cut off due to a power failure. The power supply abnormality signal reset signal generating circuit is provided with a power abnormality signal reset signal generating circuit that receives the power abnormality signal and outputs a reset signal, and a circuit that resets the power abnormality signal with the reset signal from the power abnormality signal reset signal generating circuit.

Therefore, when the power control device according to the present invention is used, the alarm signal is disabled when there is no power-on signal, and when the power is turned on again after an alarm occurs, the alarm signal is reset independently of the power-on signal line. This makes it possible to prevent the conventional pulsed power output from occurring before the power output becomes constant.

〔Example〕

The present invention will be described in detail with reference to Examples below.

FIG. 1 is a block diagram showing the power supply control device of this embodiment, and FIG. 2 is a diagram showing its operation timing chart. The same parts as in FIGS. 3 and 4 are designated by the same reference numerals, and their description will be omitted as appropriate.

In the figure, an on/off signal 12 for a power supply 11 from a host device (not shown) is applied to one input terminal of an AND circuit 15 constituting a power source control circuit 14 of a power supply control device 13. The ON/OFF signal 16 outputted from the AND circuit 15 is sent to the power supply 11, and thereby the power supply 11 provides an output voltage vout. The other input terminal of the AND circuit 15 is configured to take a negative value. The alarm signal 17 from the power supply 11 is connected to this negative input terminal.
It passes through the AND circuit 18, which is a feature of the present invention, to become the second alarm signal 19, and further passes through the latch circuit 20 to the third alarm signal.
It is input as an alarm signal 21.

The other input terminal of the AND circuit 18 is connected to the power supply control circuit 14.
The input/disconnection signal 16, which is the output of the AND circuit 15, is branched and input manually. When this closing/cutting signal 16 is not a closing signal, a logic 0 level is input to the AND circuit 18, so even if the first alarm signal 17 is present, the second alarm signal 19 becomes 0, and the alarm is invalid. It will be the same as not having . This alarm is enabled only when the closing/cutting signal 16 is a closing signal. The latch circuit 20 is used when the power supply 11 is turned on again after it has been cut off due to a power failure. That is,
When the alarm reset signal generation circuit 24 receives the input/disconnection signal 12 from a host device (not shown), the alarm reset signal generation circuit 24 sends out a reset signal 25 to the latch circuit 20. Upon receiving this, the latch circuit 20 resets the second alarm signal 19. That is, the second
When the alarm signal 19 is 1, its output, the third alarm signal 21, is 0. Furthermore, when the power-on is completed, a power-on completion signal 26 is sent from the power supply 11 to the power supply control circuit 1.
4, thereby giving a constant output from the power supply 11■. Ll
□ is given.

Next, the operation of this device will be explained with reference to FIG.

When a closing instruction is given by a closing/cutting signal 12 from a host device (not shown) (see FIG. 2a), the A N D circuit 1
A power supply signal is applied to the power supply 11 from the power supply 11 by the power supply/disconnection signal 16 (FIG. 2C). This results in power output■. U.T.
(Fig. 2b) increases with the passage of time and eventually reaches a constant value. When the value reaches a certain value, a power-on completion signal 26 (FIG. 2 d) is applied from the power supply 11 to the power supply control circuit 14, and the power-on is completed. In this case, the first alarm signal (e) in FIG. 2 and the third alarm signal 21 (f in FIG. 2) are at 0 level, assuming that there is no fault in the power supply 11.

Here, it is assumed that some kind of failure has occurred in the power supply 11.

In this case, the alarm signal 17 becomes level 1. In other words, an alarm is generated (Fig. 2e). In this state, the closing/cutting signal 12.16 remains turned on (second
Figures a, c). Therefore, the ON/OFF signal 16 at level 1 and the first alarm signal 17 are input to the AND circuit 18, and the second alarm signal 19 also becomes level 1. Since the latch circuit 20 is not operating in this case, the second alarm signal 19 directly becomes the third alarm signal 21 (FIG. 2f), and is input to the negative input terminal of the AND circuit 15 of the power supply control circuit 14. Since the other input terminal of this AND circuit 15 is input with the level 1 closing/cutting signal 12, the closing/cutting signal 16 which is the output of this AND circuit 15 is at level 0 (Fig. 2C ). Therefore, the power supply 11 is disconnected and its output voltage ■. UT becomes 0 (Figure 2b).

Next, a case will be described in which a failure occurs in the power supply 11 as described above, the power supply 11 is cut off by issuing the alarm signal 17, and then the power supply 11 is turned on again from a host device (not shown).

In this case, the power supply control circuit 14 is connected to the host device (not shown).
The ON/OFF signal 12 is connected to one terminal of the AND circuit 15 of
An input signal is given as (FIG. 2d). In this state, the first alarm signal 17, and therefore the second alarm signal 19, are at level 1 (Fig. 2e), and unless this is released, re-input is not possible. Therefore, the input/disconnection signal 1
2 is branched and applied to the alarm reset signal generation circuit 24. As a result, this alarm reset signal generation circuit 24 gives a reset signal 25 to the latch circuit 20, and this latch circuit 20 resets the second alarm signal 19 and gives a third alarm signal 21 at level 0 ( Figure 2 f). The AND circuit 15 receiving this,
On the other hand, since the input/disconnection signal 12 is received, the level is 1.
Sends the on/off signal 16 to the power supply 11 (Fig. 2C)
).

As a result, the power supply 11 is turned on again, and its output voltage vou
t increases (Fig. 2b). Then, the input completion signal 2
6 (FIG. 2 d) is sent to the power supply control circuit 14, and the reinsertion operation is completed.

〔Effect of the invention〕

In this way, the power supply control device of the present invention disables the alarm signal when there is no power-on signal, and resets the alarm signal regardless of the power-on signal line when the power is turned on again after the power failure is removed. This has the effect of being able to eliminate the effects of resetting that occurs before the power output becomes constant.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a power supply control device according to the present invention, FIG. 2 is an operation timing diagram thereof, FIG. 3 is a block diagram showing a conventional power supply control device, and FIG. 4 is an operation timing diagram thereof. It is. 11...Electric power! Original, 18...AND circuit,
20...Latch circuit, 24...Alarm reset signal generation circuit. Applicant NEC Corporation Agent
Patent Attorney Umeo Yamauchi Figure 1

Claims (1)

[Claims] In a power supply control device that controls power on, off, abnormality processing, etc. used in information processing equipment, etc., there is a circuit that enables the power supply abnormality signal while the power supply signal is being applied, and a circuit that enables the power supply abnormality signal when the power supply failure occurs. a power supply abnormality signal reset signal generation circuit that outputs a reset signal in response to a power-on signal from a host device, etc. when the power is turned on again after being cut off;
A power supply control device comprising: a circuit for resetting the power supply abnormality signal using a reset signal from the power supply abnormality signal reset signal generating circuit.