JPH01201946A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01201946A JPH01201946A JP63026015A JP2601588A JPH01201946A JP H01201946 A JPH01201946 A JP H01201946A JP 63026015 A JP63026015 A JP 63026015A JP 2601588 A JP2601588 A JP 2601588A JP H01201946 A JPH01201946 A JP H01201946A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- circuit board
- printed circuit
- leads
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にリードの形状に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the shape of a lead.
従来、リードがパッケージの底部に下方に向けられて複
数並設された半導体装置は、シングルラインパッケージ
型半導体装置と呼ばれ、基板のスルーホールにリードの
先端部が挿入され、基板に立てられた状態に実装されて
いる。これを図によって説明する。第５図は従来のこの
種ジグザグインラインパッケージ型半導体装置を一部を
破断して示す斜視図、第６図は側面図、第７図は基板に
実装された状態を一部を断面して示す側面図で、これら
の図において、１はジグザグインラインパッケージ型半
導体装置本体、２はＩＣチップ、３はこのＩＣチップ２
を支持するダイパッドで、とのダイパッド３上にＩＣチ
ップ２がろう材４によって固着されている。５はリード
、６はこのリード５と前記ＩＣチップ２の電極（図示せ
ず）とを接続するための金属細線で、リード５における
金属細線６と接合される部位には、接続が確実に行なわ
れるようにＡｇメツキ等のメツキ７が施されている。ま
た、前記リード５は後述するモールド樹脂によってパッ
ケージが形成されてからリードフレーム（図示せず）よ
シ分断され、パッケージよシ突出する先端部５ａは互い
に隣り合うリード５どうしが離間するように形成されて
いる。すなわち、互いに隣り合う各リード５の先端部５
ａは、リード５が並設される方向と直交する方向であつ
て、各リードの向きと直交する方向に一定間隔を保持す
るように折シ曲げられている。Conventionally, a semiconductor device in which multiple leads were arranged in parallel at the bottom of the package with the leads facing downwards was called a single-line packaged semiconductor device. Implemented in state. This will be explained using a diagram. FIG. 5 is a partially cutaway perspective view of a conventional zigzag in-line packaged semiconductor device of this type, FIG. 6 is a side view, and FIG. 7 is a partially cutaway view of the semiconductor device mounted on a board. In these figures, 1 is a zigzag in-line package type semiconductor device body, 2 is an IC chip, and 3 is this IC chip 2.
The IC chip 2 is fixed onto the die pad 3 by a brazing material 4. Reference numeral 5 indicates a lead, and reference numeral 6 indicates a thin metal wire for connecting the lead 5 to an electrode (not shown) of the IC chip 2. The portion of the lead 5 to be joined to the thin metal wire 6 must be connected reliably. Plating 7, such as Ag plating, is applied to ensure that the surface is protected. Further, the leads 5 are separated by a lead frame (not shown) after a package is formed using a molding resin, which will be described later, and the tips 5a protruding from the package are formed so that adjacent leads 5 are separated from each other. has been done. That is, the tips 5 of the leads 5 adjacent to each other
A is a direction perpendicular to the direction in which the leads 5 are arranged in parallel, and is bent so as to maintain a constant interval in the direction perpendicular to the direction of each lead.
８は前記ＩＣチップ１および金属細線６等を封止し、か
つ外力よシ保護するパッケージを構成するモールド樹脂
である。Reference numeral 8 denotes a molding resin constituting a package that seals the IC chip 1, the thin metal wire 6, etc., and protects it from external forces.
このように構成された半導体装置は第７図に示すように
実装される。同図において９はプリント基板、１０はス
ルーホールで、このスルーホール１０はプリント基板９
の表面に形成された配線パターン（図示せず）によって
他の装置（図示せず）等に接続されている。なお、１１
は半田、１２はプリント基板９上に表面実装されたチッ
プ部品である。このプリント基板９に前記半導体装置を
実装するには、半導体装置のり一部５をプリント基板９
の上方からスルーホール１０内に挿入させ、プリント基
板９の下方からスルーホール１０内に半田を供給するこ
とによって行なわれ、半導体装置はプリント基板９に対
して立てられた状態に実装されることになる。The semiconductor device constructed in this manner is mounted as shown in FIG. In the figure, 9 is a printed circuit board, 10 is a through hole, and this through hole 10 is a printed circuit board 9.
It is connected to other devices (not shown) through a wiring pattern (not shown) formed on the surface of the device. In addition, 11
12 is solder, and 12 is a chip component surface-mounted on the printed circuit board 9. In order to mount the semiconductor device on this printed circuit board 9, a portion 5 of the semiconductor device glue is attached to the printed circuit board 9.
This is done by inserting the semiconductor device into the through hole 10 from above and supplying solder into the through hole 10 from below the printed circuit board 9, so that the semiconductor device is mounted in an upright state on the printed circuit board 9. Become.
すなわち、従来のこの種ジグザグインラインパッケージ
型半導体装置は互いに隣り合うリード５が先端部では離
間されているから、スルーホール１０どうしが干渉する
ことなくリード５の本数を増やすことができ、モールド
樹脂両端からリードが突出しているデュアルインライン
パッケージ型半導体装置に比べて実装面積を小さくでき
るという利点があった。That is, in the conventional zigzag in-line package type semiconductor device of this kind, since the adjacent leads 5 are separated from each other at the tips, the number of leads 5 can be increased without interference between the through holes 10, and both ends of the molded resin can be increased. This has the advantage that the mounting area can be reduced compared to a dual in-line package type semiconductor device in which the leads protrude from the top.
しかるに、このように構成された半導体装置を実装する
プリント基板９においては、スルーホール１０の占有面
積が大きいため、プリント基板９を小型化するために基
板９上に形成された配線パターンの配線密度を上げるに
は限度があった。However, in the printed circuit board 9 on which the semiconductor device configured as described above is mounted, the area occupied by the through holes 10 is large, so the wiring density of the wiring pattern formed on the circuit board 9 is reduced in order to downsize the printed circuit board 9. There was a limit to how much it could rise.
また、半田１１がプリント基板９の裏面から供給される
ため、プリント基板９上にチップ部品１２等の他の表面
実装部品が混載される場合には、プリント基板９を裏返
して半田付けしなければならず、半田付は作業が煩雑に
なるという問題があった。Furthermore, since the solder 11 is supplied from the back side of the printed circuit board 9, when other surface mount components such as chip components 12 are mixedly mounted on the printed circuit board 9, the printed circuit board 9 must be turned over and soldered. However, there was a problem in that the soldering work was complicated.
本発明に係る半導体装置は、リードの先端部をＵ字状に
折曲げ形成し、半田付は部を設けたものである。In the semiconductor device according to the present invention, the tips of the leads are bent into a U-shape, and a soldering section is provided.
リードが基板の配線パターン上に半田付けされ、半導体
装置は基板に表面実装される。The leads are soldered onto the wiring pattern of the board, and the semiconductor device is surface mounted on the board.
以下、その構成等を図に示す実施例によシ詳細に説明す
る。Hereinafter, the configuration and the like will be explained in detail with reference to the embodiment shown in the drawings.
第１図は本発明に係る半導体装置を示す斜視図、第２図
は側面図、第３図は基板に実装された状態を一部を断面
して示す側面図、第４図は他の実施例を示す側面図であ
る。これらの図において前記従来例で説明したものと同
一もしくは同等部材については同一符号を付し、ここに
おいて詳細な説明は省略する。これらの図において、２
１はリード５の先端部５ａに設けられた半田付は部で、
この半田付は部２１はリード５の先端が上方を指向する
よう先端部５ａをＵ字状に折曲げることによって形成さ
れている。FIG. 1 is a perspective view showing a semiconductor device according to the present invention, FIG. 2 is a side view, FIG. 3 is a partially sectional side view showing a semiconductor device mounted on a substrate, and FIG. 4 is a diagram showing another embodiment. It is a side view which shows an example. In these figures, the same or equivalent members as those explained in the conventional example are given the same reference numerals, and detailed explanation will be omitted here. In these figures, 2
1 is the soldering part provided at the tip 5a of the lead 5;
This soldering part 21 is formed by bending the tip 5a of the lead 5 into a U-shape so that the tip of the lead 5 is directed upward.
このように形成された半田付は部２１を有する半導体装
置１をプリント基板９に実装させるには、予めプリント
基板９上にリード５と対応する配線パターン９ａを形成
しておき、第３図に示すように、この配線パターン９ａ
上にリード５の半田付は部２１を半田１１によって固着
させればよい。In order to mount the semiconductor device 1 having the soldering portion 21 thus formed on the printed circuit board 9, a wiring pattern 9a corresponding to the leads 5 is formed on the printed circuit board 9 in advance, and as shown in FIG. As shown, this wiring pattern 9a
To solder the lead 5 on the top, the portion 21 may be fixed with the solder 11.
したがって、本発明に係る半導体装置はプリント基板９
上にスルーホールを使用せずに表面実装されることにな
るから、プリント基板９上の配線パターン９ａの配線密
度を上げることができ、また、プリント基板９の表面側
から半田付けされることになる。Therefore, the semiconductor device according to the present invention has a printed circuit board 9
Since it is surface mounted without using a through hole on the top, it is possible to increase the wiring density of the wiring pattern 9a on the printed circuit board 9, and it is also possible to solder from the surface side of the printed circuit board 9. Become.
なお、上記実施例ではリード５の先端を先端部５ａよシ
内側に向けて折曲げることによって半田付は部２１を形
成した例を示したが、第４図に示すように形成すること
もできる。すなわち、第４図は他の実施例を示し、同図
において半田付は部２１はリード５の先端を先端部５ａ
よシ外側に向けて形成されておシ、このように形成して
も同等の効果が得られる。In the above embodiment, the soldering part 21 is formed by bending the tip of the lead 5 inward from the tip 5a, but it can also be formed as shown in FIG. . That is, FIG. 4 shows another embodiment, in which the soldering part 21 connects the tip of the lead 5 to the tip 5a.
Although it is formed facing outward, the same effect can be obtained even if it is formed in this way.
以上説明したように本発明によれば、リードの先端部を
Ｕ字状に折曲げ形成し、半田付は部を設けたため、リー
ドは基板の配線パターン上に半田付けされることになシ
、スルーホールが不要になるから、配線パターンの配線
密度を上げることができ基板の小型化が実現されると共
に、同種のＱＦＰ型半導体装置に比べ実装密度を向上さ
せることができる。As explained above, according to the present invention, the tip of the lead is bent into a U-shape and a soldering section is provided, so that the lead is not soldered onto the wiring pattern of the board. Since no through holes are required, the wiring density of the wiring pattern can be increased, the size of the board can be reduced, and the packaging density can be improved compared to the same type of QFP type semiconductor device.
また、半導体装置は基板に表面実装されることになシ、
基板の表面側から半田が供給され半田付けされることに
なるから、基板上に他の表面実装部品が混載される場合
でも基板を裏返して半田付けする必要がないので、半田
付はプロセスを簡略化することができるという効果もあ
る。Also, semiconductor devices are not meant to be surface mounted on a substrate.
Since the solder is supplied from the front side of the board, even if other surface mount components are mounted on the board, there is no need to turn the board over and solder, simplifying the soldering process. It also has the effect of being able to be transformed into
第１図は本発明に係る半導体装置を示す斜視図、第２図
は側面図、第３図は基板に実装された状態を一部を断面
して示す側面図、第４図は他の実施例を示す側面図、第
５図は従来のジグザグインラインパッケージ型半導体装
置を一部を破断して示す斜視図、第６図は側面図、第７
図は基板に実装された状態を一部を断面して示す側面図
である。
１・・・・半導体装置、５・・・・リード、５ａ・・・
・先端部、８・・・・モールド樹脂、２１・・・・半田
付は部。FIG. 1 is a perspective view showing a semiconductor device according to the present invention, FIG. 2 is a side view, FIG. 3 is a partially sectional side view showing a semiconductor device mounted on a substrate, and FIG. 4 is a diagram showing another embodiment. A side view showing an example, FIG. 5 is a partially cutaway perspective view of a conventional zigzag in-line package type semiconductor device, FIG. 6 is a side view, and FIG.
The figure is a partially sectional side view showing the state in which the device is mounted on a board. 1...Semiconductor device, 5...Lead, 5a...
・Tip part, 8...Mold resin, 21...Soldering part.
Claims (1)
設され、互いに隣り合うリードのそれぞれの先端部がリ
ードの並設方向と直交する水平方向に離間された半導体
装置において、前記リードの先端部をＵ字状に折曲げ形
成し、半田付け部を設けたことを特徴とする半導体装置
。In a semiconductor device in which a plurality of leads are arranged in parallel downwardly at the bottom of a package, and the tips of the adjacent leads are spaced apart in a horizontal direction perpendicular to the direction in which the leads are arranged in parallel, A semiconductor device characterized by being bent into a U-shape and provided with a soldering part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63026015A JPH01201946A (en) | 1988-02-05 | 1988-02-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63026015A JPH01201946A (en) | 1988-02-05 | 1988-02-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01201946A true JPH01201946A (en) | 1989-08-14 |
Family
ID=12181869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63026015A Pending JPH01201946A (en) | 1988-02-05 | 1988-02-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01201946A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100393926B1 (en) * | 1997-06-30 | 2003-11-28 | 오끼 덴끼 고오교 가부시끼가이샤 | Mounting structure for electronic parts |
-
1988
- 1988-02-05 JP JP63026015A patent/JPH01201946A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100393926B1 (en) * | 1997-06-30 | 2003-11-28 | 오끼 덴끼 고오교 가부시끼가이샤 | Mounting structure for electronic parts |
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