JPH01202016A - Monostable multivibrator - Google Patents

Abstract

PURPOSE:To accurately obtain objective output pulse width by determining the output pulse width by a clock interval to be impressed to a clock input of a variable length shift register and a value set by an external shift length input of a variable length shift register. CONSTITUTION:The title device consists of an SR latch 3 and a maximum length N (N>=n) variable length shift register 4 capable of setting up length n (n: integer) by an external shift length input. The output of the SR latch 3 is connected to the input of the register 4 and the output of the register 4 is connected to the reset input of the SR latch 3. A pulse input and a pulse output are respectively used as the set input of the SR latch 3 and an SR latch output and the output pulse width is determined by a clock interval to be impressed to the clock input of the register 4 and a value (n) set up by the external shift length input of the register 4. Consequently, the objective output pulse width can be accurately obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to the fields of communication devices, digital computers, etc. that apply digital logic circuits, and particularly to logic circuits and integrated circuits constructed using individual electronic components. This invention relates to mono-multivibrators used in all fields of designing digital equipment using the logic circuits that constitute them.

[Conventional technology]

Generally, monomultivibrators are designed to apply an input pulse and then obtain an arbitrary defined output pulse width. And the conventional mono-multivibrator is
This objective is achieved by setting a time constant based on the integral action of the pulse.

In other words, in an integrating circuit consisting of one resistor and one capacitor, a predetermined voltage source, for example, a power supply, is connected and integrated from the input pulse application time, and the integrated voltage reaches a predetermined value. is designed to obtain the output pulse width during this period. Generally, mono-multivibrators are developed and commercially available as individual components integrated into integrated circuits.

An example of a conventional mono-multivibrator of this type is shown in FIG. 3 and will be described.

In the figure, 11 is a pulse input terminal, 12 is an integrated mono-multivibrator that connects this pulse input terminal 11 to terminal A, and 13 is this integrated mono-multivibrator 1.
14 is an external resistor connected between terminal R/C and terminal R of the integrated mono-multivibrator 12; 15 is an external resistor connected to the terminal Q of the integrated mono-multivibrator 12; An external capacitor 16 connected between terminal R/C and terminal C is a +5V voltage source.

In the mono-multivibrator configured in this way, the external resistor 14 and the external capacitor 15 are selected, and the output pulse width is obtained in relation to the time constant obtained by the product thereof.

[Problem to be solved by the invention]

In the conventional mono-multivibrator described above, the output pulse width depends on the time constant and voltage source. Since this voltage source generally becomes the power supply voltage when the mono-multivibrator is integrated, the output pulse width cannot be made variable by the voltage source. Furthermore, the values of resistors and capacitors are generally fixed, and the output pulse damage for these values is also fixed.

Therefore, in applications where a target pulse width is obtained by external control, there is a problem of lack of flexibility. Further, the above-mentioned time constant is determined by each resistor and capacitor, but due to their "dispersion", there is a problem that it is not possible to accurately obtain the desired output pulse width.

[Means to solve the problem]

The mono multivibrator of the present invention consists of one SR latch and a variable length shift register with a maximum length N (N>n) whose length n (n: integer) can be set by an external shift length input. , the output of the SR latch is connected to the input of the variable length shift register, the output of the variable length shift register is connected to the reset input of the SR latch, the pulse input is used as the set input of the SR latch, and the pulse output is The output pulse is an SR latch output, and the corner of the output pulse can be determined by the clock interval applied to the clock input of the variable length shift register and the value n set by the external shift length input of the variable length shift register.

[Effect]

In the present invention, the digital value is basically the number of clocks and the number of variable-length shift register stages, and the number of shift register stages can be given as a digital value, and can also be given as an arbitrary time constant depending on the precision of the shift clock, the clock frequency, etc. The time constant can be changed flexibly by simply converting the clock frequency in conjunction with the shift register stage.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a mono-multivibrator according to the invention.

In the figure, 1 is a pulse input terminal that applies the input pulse of the multivibrator, 2 is a clock input terminal, and 3 is an S such as a flip-flop that can be set and reset.
R latch, 4 is a maximum length N (N2n) variable length shift register whose length n (n: integer) can be set by external shift length input, 5 is a pulse output terminal for obtaining the output pulse of the multivibrator, 6 -0.6-1...6(i
-1) is an external shift length setting input terminal for externally controlling the shift length.

The pulse input terminal 1 is connected to the set terminal S of the SR latch 3, and the Q output of this SR latch 3 is connected to the pulse output terminal 5 and the variable length shift register 40.
The clock input terminal 2 is connected to the clock terminal CLK of a variable length shift register 4, and the Q output of this variable length shift register 4 is connected to the reset terminal R of the SR latch 3. In addition, external shift length setting input layer elements 6-0.6-1...6-(i-1) are terminals AO, Al...Φ・A(
1-1) respectively.

Thus, the output of SR latch 3 is connected to the input of variable length shift register 40, and the output of variable length shift register 4 is SR? It is connected to the reset input of Tsuchi3, the pulse input is set to SR9R2SO4, and the pulse output is set to S
The output pulse width of the R ratte 3 is the value n set by the clock interval applied to the clock input of the variable length shift register 4 and the external shift length input of the variable length shift register 4.
It is configured such that it can be determined by

Figure 2 is a time chart used to explain the operation of Figure 1.
(a) shows the pulse input, (C) shows the pulse output, and (d) shows the variable length shift register output.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

First, input pulse from pulse input terminal 1 (see Fig. 2 (a)
) is input to the SR latch 30 set terminal SIC. From this moment on, the pulse output terminal 5 begins to output output pulses (
See Figure 2(c). This signal is routed to a variable length shift register 40 input terminals whose length is set to
The clock shifts every time a clock (see Figure 2) is input from the clock input terminal 2, and when n clock pulses are input, it appears from the output of the variable length shift register 4 (see Figure 2). (see (d)). This signal is SR
Since it is connected to the reset terminal R of the latch 2, the latch output, that is, the output pulse of the pulse output terminal 5 stops. By the way, the variable length shift register 4 has one setting input of external shift length input terminals 6-θ to 6-L (1-1).

Therefore, the shift length n representing a decimal number can be represented by an l-bit binary number added from this one input. In this case, the maximum length N can take values up to N=2i. For example, if i=8, the maximum is N=256. At this time, as an example of the correspondence between decimal numbers and binary numbers, Jo: n
2 + i (to and nz are decimal and binary representation values, respectively), then nl. represents the number of shifts from 1 to 256 steps.

Next, the 1 pulse output (see Figure 2 (e)) samples the output of the SR latch 3, so due to the sampling error, it is not exactly n criso 2 minutes, but a width of n from (n-1). becomes. Here, when n is large, the error becomes small. In any case, the pulse output is realized by clock frequency control and the number of stages (shift length) of the variable length shift register 4 instead of the time constant in the prior art.

[Effects of the Invention] As explained above, the present invention uses all logic circuits as a circuit configuration, and eliminates analog values such as time constants using resistors and capacitors and voltage source determination in the conventional technology. Instead, more accurate digital values are based on the number of clocks and the number of variable length shift register stages.

In addition to the number of shift register stages, which can be given as a digital value, it is also possible to give an arbitrary time constant more precisely depending on the input power such as the precision of the shift register, the clock frequency, etc., and it is flexible by simply converting the clock frequency in conjunction with the shift register stage. In particular, changing the time constant has a different effect.

Further, the present invention is extremely effective in that it is easy to convert into a digital integrated circuit because it is entirely a digital circuit and does not require resistors or capacitors.

[Brief explanation of the drawing]

Fig. 1 is a circuit configuration diagram showing an embodiment of a mono multivibrator according to the present invention, Fig. 2 is a time chart for explaining the operation of Fig. 1, and Fig. 3 is a circuit configuration diagram showing an example of a conventional mono multivibrator. It is a diagram. 1...Pulse input terminal, 2...Clock input terminal, 3...@SR latch, 4φ...Variable length shift register, 5...Pulse output terminal, 6-θ~6= (1
-1)...External shift length setting input terminal.

Claims (1)

[Claims] It consists of one SR latch and a maximum length N (N≧n) variable length shift register whose length n (n: integer) can be set by an external shift length input, and the output of the SR latch is The output of the variable length shift register is connected to the reset input of the SR latch, the pulse input is the set input of the SR latch, the pulse output is the SR latch output, and the output pulse width is can be determined by a clock interval applied to a clock input of the variable length shift register and a value n set by an external shift length input of the variable length shift register.