JPH01202920A - Logic circuit - Google Patents

Abstract

PURPOSE:To output a signal being the inversion of a signal given to a gate of a transistor(TR) placed most closely to the power supply by utilizing the TR closest to the power supply among stacked longitudinally and providing a TR having the same gate input as that of the TR and an output signal in common to that of the TR in the complementary relation. CONSTITUTION:The circuit consists of a NOR circuit NORing input signals A, B and giving the result as an output signal O1, a 1st TR 1 of P-channel placed closest to the power supply among the longitudinally stacked TRs being a component of the NOR circuit, and a 2nd TR 5 of N-channel having the same gate input as that of the TR 1 in the complementary relation to the TR 1, and also a NOT circuit taking the inversion of the input signal A and outputting the result as an output signal O2. Then with the signals A, B in the relation of A=0, B=0, the signals O1, O2 go to '1'. Moreover, with the signals A, B in the relation of A=0, B=1, the signals O1 goes to '0' and the signal O2 goes to '1'. Then with the signals A, B in the relation of A=1, B=0, and A=1, B=1 the signals O1, O2 go to '0'. Thus, the signal O1 is a NOR output of the signals A, B and the signal O2 is a NOT logic output of the signal A.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit, and more particularly to a logic circuit with a large number of outputs and a large number of circuits formed of semiconductor integrated circuits.

[Conventional technology]

Conventionally, this type of logic circuit has been comprised of a first circuit that outputs logic composed of multiple input signals, and a second circuit that outputs an inverted signal of the multiple input signals.

FIG. 5 is a circuit diagram showing an example of a conventional logic circuit.

As shown in FIG. 5, a NOR circuit consisting of a P-channel type transistor 6.7 and an N-channel type transistor 8.9 that performs the NOR of input signals A and B and outputs an output signal 01; It is composed of a NOT circuit consisting of a P-channel type transistor 10 and an N-channel type transistor 11, which take the negative logic of the input signal A and output the output signal 02.

FIG. 6 is a diagram showing truth values of the logic circuit of FIG. 5.

[Problem to be solved by the invention]

In addition to outputting a logic composed of multiple input signals, the conventional logic circuit described above also outputs an inverted signal of any input signal among the input signals. The disadvantage is that a circuit is required to output the .

[Means to solve the problem]

The logic circuit of the present invention is a semiconductor integrated circuit that outputs logic composed of multiple input signals, and in the semiconductor integrated circuit, a first transistor closest to a power supply in a vertical radiator and a first transistor and a second transistor having the same gate input and in a complementary relationship, and a circuit that outputs an inverted signal of the gate input.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

As shown in FIG.
A first P-channel type transistor 1, which is a vertical product transistor that forms part of an OR circuit and is closest to the power supply, and a second N-channel type transistor 5, which has the same gate input as the transistor 1 and has a complementary relationship. NOT, which takes the inverted logic of input signal A and outputs it as output signal 02.
circuit.

FIG. 2 is a diagram showing truth values of the first embodiment of FIG. 1.

1 and 2, input signals A and B are A=O,
When B=0, P-channel transistors 1 and 2 become conductive, and N-channel transistors 3 and 4.5 become conductive.
becomes non-conductive, and the output signal O1 is output from transistor 1.
The output signal 02 becomes 1"' through the transistor 1.

When input signals A and B are A=O, B=1, transistor 1
and transistor 4 becomes conductive, transistor 2 and transistor 3.5 become non-conductive, and the output signal O1
becomes “O”° through transistor 4, and output signal 0
2 becomes 1'' through the transistor].

Input signals A and B are A=1. When B=O, transistor 2
, transistors 3 and 5 become conductive, transistor 1 and transistor 4 become non-conductive, and the output signal 01
becomes °゛0'' through transistor 3, and output signal 0
2 becomes '°0'' through transistor 5.

Input signals A and B are A=1. When B=1, transistor 3
~5 becomes conductive, transistor 1.2 becomes non-conductive, the output signal 01 becomes 0° through transistor 3.4, and the output signal 02 becomes 0° through transistor 5.

Therefore, the output signal O becomes the NOR output of the input signals A and H, and the output signal 0□ becomes the NOR output of the input signal A.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

As shown in the third figure, a NAND circuit that performs a NAND operation on input signals A and B and outputs it as an output signal 01a;
It forms part of a NAND circuit, and includes a NOT circuit that takes the inverted logic of input signal A and outputs it as output signal 02.

FIG. 4 is a diagram showing truth values of the second embodiment of FIG. 3.

In FIGS. 1 and 2, input signals A and B are A=0.
When B=O, P-channel type transistors 1.2, 1.
3.16 becomes conductive, the N-channel type transistor 14.15 becomes non-conductive, the output signal 01a becomes "°1'° through the transistor 12.13, and the output signal 02 becomes "°1'" through the transistor 16. Become.

When input signals A and B are A=O, B=1, transistor 1
2.16 and transistor 14 become conductive, transistor 13 and transistor 15 become non-conductive, output signal 018 becomes "1'° through transistor 12, and output signal 02 becomes "1"° through transistor 16.
becomes.

Input signals A and B are A=1. When B=O, transistor 1
3 and transistor 15 are in a conductive state, transistors 12, 1.6 and transistor 14 are in a non-conductive state,
Output signals 0 and 3 become 1°' through transistor 13, and output signal 02 becomes 1°' through transistor 15.
'.

Input signals A and B are A=1. When B=1, transistor 1
4.15 becomes conductive, and transistors 12, 13 .
16 becomes non-conductive, the output signal 011 becomes "0°" through the transistors 14 and 15, and the output signal 02 becomes "0" through the transistor 15.

Therefore, output signal 0.1 becomes the NAND output of input signals A and B, and output signal 02 becomes the NAND output of input signal A.

〔Effect of the invention〕

As explained above, the present invention utilizes the transistor closest to the power supply as a vertical stack transistor in a semiconductor integrated circuit that performs logical operations on multiple input signals, and has the same gate input as that transistor and has a complementary relationship. By having a common output signal with the transistor, it has the effect of outputting logic composed of multiple input signals, and also outputting an inverted signal of the signal input to the gate of the transistor closest to the power supply using a vertical product transistor. .

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
3 is a circuit diagram of the second embodiment of the present invention; FIG. 4 is a diagram showing the truth value of the second embodiment of FIG. 3; FIG. 5 is a circuit diagram of an example of a conventional logic circuit, and FIG. 6 is a diagram showing truth values of the logic circuit of FIG. 1.2, 6, 7, 10, 12, 13.16... P-channel transistor, 3-5, 8, 9° 11.14.
15...N-channel transistor, A, B...
Input signal, 01. Ot-, O□...Output signal.

Claims (1)

[Claims] A semiconductor integrated circuit that outputs logic composed of multiple input signals, and among the semiconductor integrated circuits, a first transistor in a vertically stacked transistor closest to a power supply has the same gate input as the first transistor and has a complementary relationship. A logic circuit comprising a circuit that outputs an inverted signal of the gate input with a second transistor located at the gate.