JPH01295527A

JPH01295527A - Selecting circuit

Info

Publication number: JPH01295527A
Application number: JP63126580A
Authority: JP
Inventors: Shinichi Hirano; 平野　進一
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1988-05-23
Filing date: 1988-05-23
Publication date: 1989-11-29
Anticipated expiration: 2012-11-26
Also published as: JP2682009B2

Abstract

PURPOSE:To constitute a high speed up-down counter circuit by connecting two circuits comprising p-MOS and n-MOS transistor groups in parallel and forming its output signal as an EOR logic or an ENOR logic depending on the value of the input signal. CONSTITUTION:In case of A=0, a p-MOSTR3 is turned on and an n-MOSTR6 is turned off. In case of input signal B=0 or input signal C=0, an output O goes to logical '1' through p-MOS TRs 1, 3 and 2 and 3 or 4 and 5. In case of B=C=1, the output O goes to '0' through n-MOS TRs 10, 9 and the output O goes to an NAND logic. In case of input signal A=1, the p-MOSTR3 is turned off, the n-MOSTR6 is turned on and the circuit is operated reverse to above. Then the output signal O goes to '0' and the output signal O goes to the NOR logic. Thus, in case of input signal A=0, the NAND logic of output signals B, C is selected and in case of input signal A=1, the NOR logic of the input signals B, C is selected.

Description

【発明の詳細な説明】〔産業上の利用分野〕本発明は選択回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a selection circuit.

[Conventional technology]

従来、この種の選択回路は、２種類の論理ゲートの出力
信号を選択信号でマルチプレクスしていた、第３図は、
従来の選択回路の一例を示す接続図で、入力信号Ｂ’　
、Ｃ’のＮＡＮＤ論理信号とＮＯＲ論理信号を選択信号
Ａ′でマルチプレクスした場合を示す。Conventionally, this type of selection circuit multiplexed the output signals of two types of logic gates with the selection signal, as shown in Figure 3.
This is a connection diagram showing an example of a conventional selection circuit, in which input signal B'
, C' and the NOR logic signal are multiplexed by the selection signal A'.

第４表は第３図に示す選択回路の真理値表である。Table 4 is a truth table for the selection circuit shown in FIG.

第４表〔発明が解決しようとする課題〕上述した従来の選択回路は、２種類の論理ゲートの出力
信号を選択信号でマルチブレクスしているので、スピー
ドが低速になるという欠点がある。Table 4 [Problems to be Solved by the Invention] The conventional selection circuit described above has the disadvantage that the speed is low because the output signals of two types of logic gates are multiplexed with the selection signal.

[Means to solve the problem]

本発明の選択回路は、ソース電極に電源が供給され２つ
以上の異なるゲート入力をもつ第１の縦積みｐ−ＭＯＳ
トランジスタ群と、ソース電極に電源が供給され前記第
１の縦積みｐ−ＭＯＳ）−ランジスタ群と同じゲート入
力をもつ第２の横積みｐ−ＭＯＳトランジスタ群と、前
記第２の横積みｐ−ＭＯＳトランジスタ群の出力がソー
ス電極に供給され前自己第２の横積みｐ−ＭＯＳトラン
ジスタ群と異なるゲート入力をもつ第３のｐ−ＭＯＳト
ランジスタと、前記第１の縦積みｐ−ＭＯＳトランジス
タ群と前記第３のｐ−ＭＯＳトランジスタが共通の出力
をもち、且つ、ソース電極に接地が供給れ前記第１の縦
積みｐ−ＭＯＳトランジスタ群と同じゲート入力をもつ
第４の縦積みｎ−ＭＯＳトランジスタ群と、ソース電極
に接地が供給され前記第４の縦積みｎ−ＭＯＳトランジ
スタ群と同じゲート入力をもつ第５の横積みｎ−ＭＯＳ
トランジスタ群と、前記第５の横積みｎ−ＭＯＳトラン
ジスタ群の出力がソース電極に供給され前記第３のｐ−
ＭＯ８トランジスタと同じゲート入力をもつ第６のｎ−
ＭＯ３トランジスタと、前記第４の縦積みｎ−ＭＯ９ト
ランジスタ群と前記第６のｎ−ＭＯＳトランジスタが共
通の出力をもち、且つ、前記第１の縦積みｐ−ＭＯＳト
ランジスタ群と前記第３のｐ−ＭＯＳトランジスタの出
力が前記第４の縦積みｎ−ＭＯ３トランジスタ群と前記
第６のｎ−ＭＯ８トランジスタの出力と共通な回路とを
含んで構成される。The selection circuit of the present invention comprises a first vertically stacked p-MOS whose source electrode is supplied with power and has two or more different gate inputs.
a group of transistors, a second horizontally stacked p-MOS transistor group whose source electrodes are supplied with power and have the same gate input as the first vertically stacked p-MOS transistors; a third p-MOS transistor whose source electrode is supplied with the output of the MOS transistor group, and a third p-MOS transistor having a gate input different from that of the second horizontally stacked p-MOS transistor group; and the first vertically stacked p-MOS transistor group. a fourth vertically stacked n-MOS transistor in which the third p-MOS transistor has a common output, a ground is supplied to the source electrode, and the same gate input as the first vertically stacked p-MOS transistor group; a fifth horizontally stacked n-MOS transistor whose source electrode is supplied with ground and which has the same gate input as the fourth vertically stacked n-MOS transistor group;
The outputs of the transistor group and the fifth horizontally stacked n-MOS transistor group are supplied to the source electrode of the third p-MOS transistor group.
6th n- with same gate input as MO8 transistor
The MO3 transistor, the fourth vertically stacked n-MO9 transistor group, and the sixth n-MOS transistor have a common output, and the first vertically stacked p-MOS transistor group and the third p-MOS transistor - The output of the MOS transistor is configured to include a circuit common to the fourth vertically stacked n-MO3 transistor group and the output of the sixth n-MO8 transistor.

〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は、本発明を選択信号Ａで、出力０がＢ。In FIG. 1, the present invention is selected by a selection signal A, and output 0 is B.

ＣのＮＡＮＤ論理かＮＯＲ論理かを選択する回路に実施
した場合の第１の実施例を示す接続回路図であり、第１
表は第１図の真理値表である。2 is a connection circuit diagram showing a first embodiment when implemented in a circuit for selecting between NAND logic and NOR logic of C.
The table is the truth table of FIG.

Ａ＝Ｏの時、ｐ−ＭＯ３トランジスタ３は“ＯＮ”、ｎ
−ＭＯ３トランジスタロは’ＯＦＦ’　となり、入力信
号Ｂ＝Ｏあるいは入力信号Ｃ＝０ならば、ｐ−ＭＯＳト
ランジスタ１と３，２と３あるいは４と５を通して、出
力Ｏは“１′となり、Ｂ＝Ｃ＝１ならばｎ−ＭＯＳトラ
ンジスタ１０と９を通して、出力０は“０′となり、出
力０は、ＮＡＮＤ論理になる。When A=O, p-MO3 transistor 3 is “ON”, n
-MO3 transistor RO becomes 'OFF', and if input signal B=O or input signal C=0, output O becomes "1" through p-MOS transistors 1 and 3, 2 and 3 or 4 and 5, and B If =C=1, the output 0 becomes "0" through the n-MOS transistors 10 and 9, and the output 0 becomes NAND logic.

第１表次に、入力信号Ａ＝１の時、ｐ−ＭＯＳトランジスタ３
はＯＦＦ’　、ｎ−ＭＯ３）−ランジスタロは“ＯＮ”
となり、Ｂ＝Ｃ＝Ｏならばｐ　−Ｍ　ＯＳトランジスタ
４と５を通して、出力信号０は“１°となり、Ｂ＝１あ
るいはＣ＝１ならば、ｎ−ＭＯＳトランジスタフと６．
８と６あるいは１０と９を通して、出力信号Ｏは“０°
となり、出力信号０は、ＮＯＲ論理になる。Table 1 Next, when input signal A=1, p-MOS transistor 3
is OFF', n-MO3) - Ranjistaro is “ON”
If B=C=O, the output signal 0 becomes "1 degree" through the p-MOS transistors 4 and 5, and if B=1 or C=1, the output signal 0 becomes "1 degree" through the p-MOS transistors 4 and 5, and if B=1 or C=1, the output signal 0 becomes "1 degree" through the p-MOS transistors 4 and 5.
Through 8 and 6 or 10 and 9, the output signal O is “0°
Therefore, the output signal 0 becomes NOR logic.

従って、入力信号Ａ＝Ｏの時、出力信号Ｂ、ＣのＮＡＮ
Ｄ論理が選択され、入力信号Ａ＝１の時、入力信号Ｂ、
ＣのＮＯＲ論理が選択される。Therefore, when input signal A=O, output signals B and C are NAN
When D logic is selected and input signal A=1, input signal B,
The NOR logic of C is selected.

第２図は、本発明を選択信号Ａで、出力ｏ２が入力信号
Ｂ、ＣとＤのＡＮＤ−ＮＯＲ論理が０Ｒ−ＮＡＮＤ論理
かを選択する回路に実施した場合の第２の実施例を示す
接続回路図であり、第２表は第２図の真理値表である。FIG. 2 shows a second embodiment in which the present invention is implemented in a circuit in which the output o2 selects whether the AND-NOR logic of the input signals B, C, and D is the 0R-NAND logic using the selection signal A. This is a connection circuit diagram, and Table 2 is a truth table of FIG.

また、第３表は、第３図の入力信号りに、第１図の出力
信号Ｏを入力した場合の真理値表である。Table 3 is a truth table when the output signal O in FIG. 1 is input to the input signal in FIG. 3.

入力信号Ａ＝Ｏの時、ｐ−ＭＯＳトランジスタ１９は’
ＯＮ’　、ｎ−ＭＯＳトランジスタ２３は’ＯＦＦ”と
なり、入力信号Ｄ＝０ならばｐ−ＭＯＳトランジスタ１
８と１９を通して、さらに入力信号Ｂ＝Ｏあるいは入力
信号Ｃ＝Ｏならば、ｐ−ＭＯＳトランジスタ２０と２２
．２１と２２を通して、また、Ｂ＝Ｃ＝Ｏならばｐ−Ｍ
ＯＳトランジスタ１６と１７と１９を通して、出力信号
０２は“１゛となり、入力信号Ｄ＝１の時、入力信号Ｂ
＝１あるいは入力信号Ｃ＝１ならばｎ−ＭＯＳトランジ
スタ２９と２７あるいは２８と２７を通して、出力信号
ｏ２は０°となり、出力信号０２は、０Ｒ−ＮＡＮＤ論
理ニなる。When the input signal A=O, the p-MOS transistor 19 is '
ON', the n-MOS transistor 23 becomes 'OFF', and if the input signal D=0, the p-MOS transistor 1
If the input signal B=O or the input signal C=O, the p-MOS transistors 20 and 22
．． Through 21 and 22, and if B=C=O, then p-M
Through the OS transistors 16, 17, and 19, the output signal 02 becomes "1", and when the input signal D=1, the input signal B
=1 or input signal C=1, the output signal o2 becomes 0° through the n-MOS transistors 29 and 27 or 28 and 27, and the output signal 02 becomes 0R-NAND logic 2.

次に入力信号Ａ＝１の時、ｐ−ＭＯＳトランジスタ１１
は“ＯＦＦ”、ｎ−ＭＯＳトランジスタ２３は“ＯＮ″
となり、入力信号Ｄ＝１ならばｎ−ＭＯＳトランジスタ
２４と２３を通して、さらに入力信号Ｂ＝１あるいは入
力信号Ｃ＝１ならば、ｎ−ＭＯＳトランジスタ２８と２
７．２９と２７を通して、また、Ｂ＝Ｃ＝１ならばｎ−
ＭＯＳトランジスタ２６と２５と２３を通して、出力信
号０２は“０°となり、入力信号Ｄ＝Ｏの時、入力信号
Ｂ＝Ｏあるいは入力信号Ｃ＝０ならばｐ−ＭＯＳトラン
ジスタ２０と２２あるいは２１と２２を通して、出力信
号０２は１゛となり、出力信号０２は、ＡＮＤ−ＮＯＲ
論理になる。Next, when the input signal A=1, the p-MOS transistor 11
is “OFF” and n-MOS transistor 23 is “ON”
If the input signal D=1, it passes through the n-MOS transistors 24 and 23, and if the input signal B=1 or the input signal C=1, it passes through the n-MOS transistors 28 and 23.
7.Through 29 and 27, and if B=C=1 then n-
Through the MOS transistors 26, 25, and 23, the output signal 02 becomes 0°, and when the input signal D=O, if the input signal B=O or the input signal C=0, the p-MOS transistors 20 and 22 or 21 and 22 , the output signal 02 becomes 1゛, and the output signal 02 becomes AND-NOR
It becomes logical.

従って入力信号Ａ＝０の時、入力信号Ｂ、ＣとＤの０Ｒ
−ＮＡＮＤ論理が選択され、入力信号Ａ＝１の時、入力
信号Ｂ、ＣとＤのＡＮＤ−ＮＯＲ論理が選択される。Therefore, when input signal A=0, input signals B, C and D are 0R.
-NAND logic is selected, and when input signal A=1, AND-NOR logic of input signals B, C, and D is selected.

第２表第３表〔発明の効果〕以上説明したように本発明は、動作を高速にし、且つ、
素子数を削減できる効果がある。Table 2 Table 3 [Effects of the Invention] As explained above, the present invention enables high-speed operation and
This has the effect of reducing the number of elements.

また、第１図の選択回路は、ｕ　ｐ　−ｄ　ｏ　ｗ　ｎ
カウンタ回路のキャリ一部に使用すると効果がある。Moreover, the selection circuit in FIG.
It is effective when used as a carry part of a counter circuit.

すなわち、選択信号Ａが０のときは、ｕｐカウンタとし
て、Ａが１のときはｄ　ｏ　ｗ　ｎカウンタとして動作
する。That is, when the selection signal A is 0, it operates as an up counter, and when A is 1, it operates as a down counter.

さらに、第２図の回路の入力りに第１図の出力○を入力
すると、第３表からも明らかなように、入力信号Ａの値
によって、その出力信号０２がＥＯＲ論理（Ａ＝　１　
）あるいはＥＮＯＲ論理（Ａ＝０）になることがわかる
。従って、第１図の回路と第２図の回路を利用すること
により、高速なＵｐ　−ｄ　ｏ　ｗ　ｎカウンタ回路を
構成できる効果がある。Furthermore, when the output ○ shown in Figure 1 is input to the input of the circuit shown in Figure 2, as is clear from Table 3, the output signal 02 changes to the EOR logic (A = 1) depending on the value of the input signal A.
) or ENOR logic (A=0). Therefore, by using the circuit of FIG. 1 and the circuit of FIG. 2, it is possible to construct a high-speed up-down counter circuit.

[Brief explanation of the drawing]

第１図は本発明の第１の実施例を示す接続回路図、第２
図は本発明の第２の実施例を示す接続回路図、第３図は
従来の一例を示す接続回路図である。１〜５・・・ｐ−ＭＯＳトランジスタ、６〜１０・・・
ｎ−ＭＯＳトランジスタ、１ｌ−ＮＡＮＤ回路、１２−
ＮＯＲ回路、１３−・・インバータ、１４．１５・・・
抱き合わせトランスファー、Ａ〜Ｃ・・・入力信号、０・・・出力信号。FIG. 1 is a connection circuit diagram showing the first embodiment of the present invention;
The figure is a connection circuit diagram showing a second embodiment of the present invention, and FIG. 3 is a connection circuit diagram showing a conventional example. 1 to 5... p-MOS transistor, 6 to 10...
n-MOS transistor, 1l-NAND circuit, 12-
NOR circuit, 13-...inverter, 14.15...
Tying transfer, A to C...input signal, 0...output signal.

Claims

[Claims]

a first vertically stacked p-MOS transistor group whose source electrode is supplied with power and has two or more different gate inputs; and a first vertically stacked p-MOS transistor whose source electrode is supplied with power and has two or more different gate inputs;
A second horizontal stack p with the same gate input as the transistor group
- MOS transistor group and the second horizontally stacked p-MO
a third p-MOS transistor whose source electrode is supplied with the output of the S transistor group and which has a gate input different from that of the second horizontally stacked p-MOS transistor group; the first vertically stacked p-MOS transistor group; Third p-MO
a fourth vertically stacked n-MOS whose S transistors have a common output, whose source electrodes are supplied with ground and which have the same gate input as the first vertically stacked p-MOS transistor group;
a fifth horizontally stacked n-MOS transistor group whose source electrodes are supplied with ground and have the same gate input as the fourth vertically stacked n-MOS transistor group; and said fifth horizontally stacked n-MOS transistor. a sixth n-MOS transistor whose source electrode is supplied with the output of the group and has the same gate input as the third p-MOS transistor;
the fourth vertically stacked n-MOS transistor group and the sixth
the n-MOS transistors have a common output, and
the first vertically stacked p-MOS transistor group and the third
The output of the p-MOS transistor of the fourth vertical stack n
- A selection circuit common to the output of the MOS transistor group and the sixth n-MOS transistor.