JPH0120516B2 - - Google Patents

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Publication number
JPH0120516B2
JPH0120516B2 JP58148580A JP14858083A JPH0120516B2 JP H0120516 B2 JPH0120516 B2 JP H0120516B2 JP 58148580 A JP58148580 A JP 58148580A JP 14858083 A JP14858083 A JP 14858083A JP H0120516 B2 JPH0120516 B2 JP H0120516B2
Authority
JP
Japan
Prior art keywords
current
superconducting josephson
supplied
superconducting
takes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58148580A
Other languages
Japanese (ja)
Other versions
JPS6040594A (en
Inventor
Kazunori Myahara
Takuji Nakanishi
Masashi Yamamoto
Shuichi Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP58148580A priority Critical patent/JPS6040594A/en
Publication of JPS6040594A publication Critical patent/JPS6040594A/en
Publication of JPH0120516B2 publication Critical patent/JPH0120516B2/ja
Granted legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/44—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using super-conductive elements, e.g. cryotron

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Description

【発明の詳細な説明】 本発明は、超伝導ジヨセフソンスイツチを用い
て構成された超伝導記憶回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a superconducting memory circuit constructed using a superconducting Josephson switch.

超伝導ジヨセフソンスイツチを用いて構成され
た超伝導記憶回路として、従来、第１図を伴なつ
て次に述べる構成を有するものが提案されてい
る。 As a superconducting memory circuit constructed using a superconducting Josephson switch, one having the configuration described below with reference to FIG. 1 has been proposed.

すなわち、超伝導ジヨセフソン接合素子Ｊと、
２つの制御線Ｃ１及びＣ２とを有し、超伝導ジヨ
セフソン接合素子Ｊに２値表示で「１」及び
「０」をとる電流が「１」で供給されている状態
で、制御線Ｃ１及びＣ２に２値表示で「１」及び
「０」をとる電流が「１」で供給された場合、超
伝導ジヨセフソン接合素子Ｊが零電圧状態から有
電圧状態に転換する超伝導ジヨセフソンスイツチ
Ｇを有する。 That is, a superconducting Josephson junction element J,
It has two control lines C1 and C2, and the control lines C1 and C2 are supplied with a current of "1" that takes "1" and "0" in binary display to the superconducting Josephson junction element J. When a current that takes "1" and "0" in the binary display is supplied as "1", the superconducting Josephson junction element J switches from the zero voltage state to the energized state. have

また、超伝導ジヨセフソン接合素子Ｊと、１つ
の制御線Ｃとを有し、超伝導ジヨセフソン接合素
子Ｊに２値表示で「１」及び「０」をとる電流が
「１」で供給されている状態で、制御線Ｃに２値
表示で「１」及び「０」をとる電流が「１」で供
給された場合、超伝導ジヨセフソン接合素子Ｊ
が、零電圧状態から有電圧状態に転換する超伝導
ジヨセフソンスイツチG′を有する。 It also has a superconducting Josephson junction element J and one control line C, and a current that takes "1" and "0" in binary display is supplied to the superconducting Josephson junction element J at "1". state, if a current of "1" is supplied to the control line C that takes "1" and "0" in binary display, the superconducting Josephson junction element J
has a superconducting Josephson switch G' that changes from a zero voltage state to a voltage state.

さらに、２つのインダクタＬ１及びＬ２を有す
る。 Furthermore, it has two inductors L1 and L2.

しかして、超伝導ジヨセフソンスイツチＧの超
伝導ジヨセフソン接合素子Ｊと、インダクタＬ１
とが直列に接続されて第１の直列回路が形成さ
れ、また、超伝導ジヨセフソンスイツチG′の超
伝導ジヨセフソン接合素子Ｊと、インダクタＬ２
とが直列に接続されて第２の直列回路が形成され
ている。 Therefore, the superconducting Josephson junction element J of the superconducting Josephson switch G and the inductor L1
are connected in series to form a first series circuit, and the superconducting Josephson junction element J of the superconducting Josephson switch G' and the inductor L2
are connected in series to form a second series circuit.

そして、第１及び第２の直列回路が並列に接続
されて並列回路が形成され、その並列回路が電源
線路Ｂに介挿されている。 The first and second series circuits are connected in parallel to form a parallel circuit, and the parallel circuit is inserted into the power supply line B.

また、超伝導ジヨセフソンスイツチＧの制御線
Ｃ１を含んで電流路Ｈ１が形成され、また、超伝
導ジヨセフソンスイツチＧの制御線Ｃ２を含んで
電流路Ｈ２が形成されている。 Further, a current path H1 is formed including the control line C1 of the superconducting Josephson switch G, and a current path H2 is formed including the control line C2 of the superconducting Josephson switch G.

さらに、超伝導ジヨセフソンスイツチG′の超
伝導ジヨセフソン接合素子Ｊを含んで電流路Ｈ６
が形成されている。 Furthermore, the current path H6 includes the superconducting Josephson junction element J of the superconducting Josephson switch G′.
is formed.

以上が従来提案されている超伝導記憶回路の構
成である。 The above is the configuration of a conventionally proposed superconducting memory circuit.

このような構成によれば、次に述べる動作が得
られる。 According to such a configuration, the following operation can be obtained.

すなわち、電源線路Ｂに、２値表示で「１」及
び「０」をとる電流を「１」で電流を「１」で供
給した状態で、電流路Ｈ１及びＨ２に２値表示で
「１」及び「０」をとる電流をともに「１」で供
給すれば、超伝導ジヨセフソンスイツチＧの超伝
導ジヨセフソン素子Ｊが零電圧状態から有電圧状
態に転移し、超伝導ループに、少くとも１つの磁
束量子が取り込まれ、このことで、２値表示で
「１」及び「０」をとる情報が「１」で記憶され
たことになる。 In other words, while a current of "1" is supplied to the power supply line B, and a current of "1" is supplied to the power supply line B, a current of "1" is supplied to the current path H1 and H2, and a current of "1" is supplied to the current path H1 and H2. If a current of 1 is supplied to both the current and 0, the superconducting Josephson element J of the superconducting Josephson switch G transitions from a zero voltage state to a voltage state, and at least 1 current is applied to the superconducting loop. This means that information that takes "1" and "0" in binary representation is stored as "1".

また、このような状態から、電源線路Ｂに、２
値表示で「１」及び「０」をとる電流を「０」で
供給しても、超伝導ループに取り込まれた磁束量
子は放出されず、従つて２値表示で「１」及び
「０」をとる情報が「１」で記憶されている状態
を保持している。 In addition, from this state, 2
Even if a current with a value of "1" and "0" is supplied as "0", the magnetic flux quanta taken into the superconducting loop will not be released, and therefore the value will be "1" and "0" on the binary display. A state is maintained in which information that takes a value is stored as "1".

さらに、このような状態から、電源線路Ｂ及び
電流路Ｈ６に、２値表示で「１」及び「０」をと
る電流をともに「１」で供給すれば、超伝導ジヨ
セフソンスイツチG′の超伝導ジヨセフソン素子
Ｊが零電圧状態から有電圧状態に転移し、このた
め、超伝導ジヨセフソンスイツチG′の超伝導ジ
ヨセフソン素子Ｊに供給された電流が流れなくな
り、このことで、２値表示で「１」及び「０」を
とる情報が「１」で読出されたことになる。 Furthermore, in such a state, if currents that take "1" and "0" in the binary display are both supplied as "1" to power supply line B and current path H6, the superconducting Josephson switch G' The superconducting Josephson element J transitions from the zero voltage state to the voltage state, and as a result, the current supplied to the superconducting Josephson element J of the superconducting Josephson switch G' stops flowing, resulting in a binary display. This means that the information that takes "1" and "0" is read out as "1".

また、超伝導ループに磁束量子が取り込まれて
いる状態にあるとき、すなわち、情報が「１」で
記憶されている状態にあるとき、電源線路Ｂに２
値表示で「１」及び「０」をとる電流を「０」で
供給している状態で、電流路Ｈ１及びＨ２に、２
値表示で「１」及び「０」をともに「１」で供給
すれば、超伝導ジヨセフソンスイツチＧ１の超伝
導ジヨセフソン素子Ｊが零電圧状態から有電圧状
態に転移し、このため、いままで超伝導ループに
保持されていた磁束量子が放出され、このこと
で、２値表示で「１」及び「０」をとる情報が
「０」で記載されたことになる。 Furthermore, when the superconducting loop is in a state where magnetic flux quanta are taken in, that is, when information is stored as "1", 2
In the state where the current that takes "1" and "0" on the value display is supplied at "0", 2 is applied to the current paths H1 and H2.
If both "1" and "0" are supplied as "1" in the value display, the superconducting Josephson element J of the superconducting Josephson switch G1 transitions from the zero voltage state to the voltage state. The magnetic flux quanta held in the superconducting loop are released, and as a result, information that takes "1" and "0" in a binary representation is written as "0".

また、このような状態から、電源線路Ｂ及び電
流路Ｈ６に２値表示で「１」及び「０」をとる電
流を「１」で供給しても、超伝導ジヨセフソンス
イツチG′の超伝導ジヨセフソン接合素子Ｊは零
電圧状態から有電圧状態に転移せず、このため、
電流路Ｈ６に供給された電流が、電流路Ｈ６に流
れている状態を保ち、このことで、２値表示で
「１」及び「０」をとる情報が「０」で読出され
たことになる。 In addition, in such a state, even if a current of "1" is supplied to the power supply line B and the current path H6 that takes "1" and "0" in the binary display, the superconducting Josephson switch G' The conducting Josephson junction element J does not transition from the zero voltage state to the voltage state, and therefore,
The current supplied to the current path H6 continues to flow through the current path H6, and this means that information that takes "1" and "0" in the binary display is read out as "0". .

上述したように、第１図に示す従来の超伝導記
憶回路によれば、２値表示で「１」及び「０」を
とる情報を記憶させ、また、これを読出すことが
できる。 As described above, according to the conventional superconducting memory circuit shown in FIG. 1, it is possible to store and read out information representing "1" and "0" in binary representation.

しかしながら、第１図に示す従来の超伝導記憶
回路の場合、２値表示で「１」及び「０」をとる
情報を「１」で記憶させるとき、電源線路Ｂに
「１」で供給される電流が、予定値に確定する以
前に、電流路Ｈ１及びＨ２に電流が「１」で供給
されれば、超伝導ジヨセフソンスイツチＧの超伝
導ジヨセフソン接合素子Ｊが、それに予定値のバ
イアス電流が供給される以前に、零電圧状態から
有電圧状態に転移するため、超伝導ループに、磁
束量子が正規の量、取込まれず、誤動作を生じ
る。 However, in the case of the conventional superconducting memory circuit shown in FIG. 1, when information that takes "1" and "0" in a binary display is stored as "1", "1" is supplied to power line B. If a current of "1" is supplied to the current paths H1 and H2 before the current is determined to the predetermined value, the superconducting Josephson junction element J of the superconducting Josephson switch G will cause the bias current to reach the predetermined value. Since the superconducting loop transitions from a zero voltage state to a voltage state before the voltage is supplied, the proper amount of magnetic flux quanta is not incorporated into the superconducting loop, resulting in malfunction.

従つて、電源線路Ｂに供給する電流と、電流路
Ｈ１及びＨ２に供給する電流との間に、順序と時
間間隔とを必要とする。 Therefore, a sequence and a time interval are required between the current supplied to the power supply line B and the current supplied to the current paths H1 and H2.

また、情報が「１」で書込まれて後、電源線路
Ｂに電流が「１」で供給されている状態から
「０」に供給されている状態に転換するとき、電
流路Ｈ１及びＨ２の少くとも何れか一方に電流が
「０」で供給されていなければ、情報が「０」で
記憶されている誤動作を生じる。 Furthermore, after the information is written as "1", when the state is changed from the state in which the current is supplied to the power line B as "1" to the state in which it is supplied as "0", the current paths H1 and H2 are If a current of "0" is not supplied to at least one of them, a malfunction will occur in which information is stored as "0".

従つて、電源線路Ｂの電流を「１」から「０」
に転換させる時刻と、電流路Ｈ１及びＨ２に電流
を「１」から「０」に転換させる時刻との間に、
順序と、時間間隔を必要とする。 Therefore, the current of power supply line B is changed from "1" to "0".
Between the time when the current is changed to ``1'' and the time when the current is changed from ``1'' to ``0'' in current paths H1 and H2,
Requires order and time intervals.

従つて、第１図に示す従来の超伝導記憶回路の
場合、情報を記憶させるのに、電源線路Ｂ、及び
電流路Ｈ１及びＨ２に供給する電流を、予定の順
序で、且つ予定の時間間隔を保つている電流とし
て用意する必要があるという欠点を有していたと
ともに、高速で記憶され、またこれから読出すこ
とができない、という欠点を有していた。 Therefore, in the case of the conventional superconducting memory circuit shown in FIG. 1, in order to store information, currents are supplied to the power line B and the current paths H1 and H2 in a predetermined order and at predetermined time intervals. It has the disadvantage that it needs to be prepared as a current that maintains the current, and it also has the disadvantage that it is stored at high speed and cannot be read from it.

さらに、第１図に示す従来の超伝導記憶回路の
場合、超伝導状態に冷却するとき、超伝導ループ
に、磁束量子が予定数でない数取込まれるおそれ
を有し、そしてこのように超伝導ループに磁束量
子が取込まれれば、超伝導ジヨセフソンスイツチ
Ｇが動作する電流レベルが大幅に変動し、このた
め、情報の書込時の電流余裕度が大幅に低下す
る、という欠点を有していた。 Furthermore, in the case of the conventional superconducting memory circuit shown in FIG. If magnetic flux quanta are incorporated into the loop, the current level at which the superconducting Josephson switch G operates will fluctuate significantly, which has the disadvantage that the current margin when writing information is significantly reduced. Was.

よつて、本発明は、上述した欠点のない、新規
な超伝導記憶回路を提案せんとするもので、以
下、本発明の実施例を詳述するところから明らか
となるであろう。 Therefore, the present invention aims to propose a novel superconducting memory circuit free from the above-mentioned drawbacks, which will become clear from the detailed description of embodiments of the present invention below.

第２図は、本発明による超伝導記憶回路の実施
例を示し、次に述べる構成を有する。 FIG. 2 shows an embodiment of a superconducting memory circuit according to the present invention, which has the configuration described below.

すなわち、超伝導ジヨセフソン接合素子Ｊと、
２つの制御線Ｃ１及びＣ２とを有し、超伝導ジヨ
セフソン接合素子Ｊに２値表示で「１」及び
「０」をとる電流が「１」で供給されている状態
で、制御線Ｃ１及びＣ２に２値表示で「１」及び
「０」をとる電流が「１」で供給された場合、超
伝導ジヨセフソン接合素子Ｊが零電圧状態から有
電圧状態に転換する、第１、第２及び第３の超伝
導ジヨセフソンスイツチＧ１，Ｇ２及びＧ３を有
する。 That is, a superconducting Josephson junction element J,
It has two control lines C1 and C2, and the control lines C1 and C2 are supplied with a current of "1" that takes "1" and "0" in binary display to the superconducting Josephson junction element J. When a current that takes "1" and "0" on a binary display is supplied at "1", the superconducting Josephson junction element J changes from the zero voltage state to the voltage state. It has three superconducting Josephson switches G1, G2 and G3.

また、第１及び第２の抵抗Ｒ１及びＲ２を有す
る。 It also includes first and second resistors R1 and R2.

しかして、超伝導ジヨセフソンスイツチＧ１及
びＧ２の超伝導ジヨセフソン接合素子が直列に接
続されて第１の直列回路が形成され、また、抵抗
Ｒ１及びＲ２が直列に接続されて第２の直列回路
が形成され、そしてそれら第１及び第２の直列回
路が並列に接続されて並列回路が形成されてい
る。 Thus, the superconducting Josephson junction elements of the superconducting Josephson switches G1 and G2 are connected in series to form a first series circuit, and the resistors R1 and R2 are connected in series to form a second series circuit. are formed, and the first and second series circuits are connected in parallel to form a parallel circuit.

そしてその並列回路が電源線路Ｂに介挿されて
いる。 The parallel circuit is inserted into the power supply line B.

また、超伝導ジヨセフソンスイツチＧ３の制御
線Ｃ１の第１の端ａ１が、上述した第１の直列回
路の超伝導ジヨセフソンスイツチＧ１及びＧ２の
超伝導ジヨセフソン接合素子Ｊの接続中点に、第
２の端ａ２が、上述した第２の直列回路の抵抗Ｒ
１及びＲ２の接続中点に接続されている。 Further, the first end a1 of the control line C1 of the superconducting Josephson switch G3 is connected to the connection midpoint of the superconducting Josephson junction element J of the superconducting Josephson switches G1 and G2 of the first series circuit described above. , the second end a2 is the resistor R of the second series circuit described above.
1 and R2.

さらに、超伝導ジヨセフソンスイツチＧ１及び
Ｇ２の制御線Ｃ１が直列に接続されて第３の直列
回路が形成され、その第３の直列回路を含んで第
３の電流路Ｈ３が形成されている。 Further, the control lines C1 of the superconducting Josephson switches G1 and G2 are connected in series to form a third series circuit, and a third current path H3 is formed including the third series circuit. .

また、超伝導ジヨセフソンスイツチＧ１及びＧ
３の制御線Ｃ２が直列に接続されて第４の直列回
路が形成され、その第４の直列回路を含んで第４
の電流路Ｈ４が形成されている。 In addition, superconducting Josephson switches G1 and G
The three control lines C2 are connected in series to form a fourth series circuit, and the fourth series circuit including the fourth series circuit is
A current path H4 is formed.

さらに、超伝導ジヨセフソンスイツチＧ２の制
御線Ｃ２を含んで第５の電流路Ｈ５が形成されて
いる。 Furthermore, a fifth current path H5 is formed including the control line C2 of the superconducting Josephson switch G2.

なおさらに、超伝導ジヨセフソンスイツチＧ３
の超伝導ジヨセフソン接合素子Ｊを含んで第６の
電流路Ｈ６が形成されている。 Furthermore, superconducting Josephson switch G3
A sixth current path H6 is formed including the superconducting Josephson junction element J.

以上が、本発明による超伝導記憶回路の実施例
の構成である。 The above is the configuration of the embodiment of the superconducting memory circuit according to the present invention.

このような構成によれば、電源線路Ｂに電流が
供給されている状態で、電流路Ｈ３及びＨ４に２
値表示で「１」及び「０」をとる電流を「１」で
供給すれば、超伝導ジヨセフソンスイツチＧ１の
超伝導ジヨセフソン接合素子Ｊ１が零電圧状態か
ら有電圧状態に転移する。 According to such a configuration, while current is being supplied to the power supply line B, two currents are applied to the current paths H3 and H4.
If a current of "1" is supplied with a value of "1" and "0" in the value display, the superconducting Josephson junction element J1 of the superconducting Josephson switch G1 transitions from the zero voltage state to the voltage state.

このため、いままで直列回路Ｇ１の超伝導ジヨ
セフソン接合素子Ｊに流れていた電流が、抵抗Ｒ
１を通つて超伝導ジヨセフソンスイツチＧ３の制
御線Ｃ１に、その一端ａ２側から他端ａ１側に向
つて流れる。そしてこのことで、２値表示で
「１」及び「０」をとる情報が、「１」で記憶され
たことになる。 For this reason, the current that has been flowing through the superconducting Josephson junction element J of the series circuit G1 is now reduced to the resistance R.
1 to the control line C1 of the superconducting Josephson switch G3 from one end a2 side to the other end a1 side. As a result, information that takes "1" and "0" in binary display is stored as "1".

また、電源線路Ｂに電流が供給されている状態
で、電流路Ｈ３及びＨ５に、２値表示で「１」及
び「０」をとる電流を「１」で供給すれば、超伝
導ジヨセフソンスイツチＧ２の超伝導ジヨセフソ
ン接合素子Ｊが零電圧状態から有電圧状態に転移
する。 In addition, if a current of "1" is supplied to current paths H3 and H5 with a current of "1" and "0" on a binary display while a current is being supplied to power line B, superconducting Josephson The superconducting Josephson junction element J of switch G2 transitions from the zero voltage state to the voltage state.

このため、いままで超伝導ジヨセフソンスイツ
チＧ２の超伝導ジヨセフソン接合素子Ｊに流れて
いた電流が、直列回路Ｇ３の制御線Ｃ１に、その
一端ａ１側から他端ａ２側に流れる。そしてこの
ことで、２値表示で「１」及び「０」をとる情報
が、「０」で記憶されたことになる。 Therefore, the current that has been flowing through the superconducting Josephson junction element J of the superconducting Josephson switch G2 flows through the control line C1 of the series circuit G3 from one end a1 to the other end a2. As a result, information that takes "1" and "0" in binary display is stored as "0".

さらに、上述したように、情報が「０」で記憶
されている状態になつてから、電流路Ｈ３及びＨ
４に供給されている電流が「０」から「１」に転
換しても、超伝導ジヨセフソンスイツチＧ１の超
伝導ジヨセフソン接合素子Ｊが有電圧状態を保つ
ているので、情報が「１」で記憶されている状態
が保持されている。 Furthermore, as described above, after the information is stored as "0", the current paths H3 and H
Even if the current supplied to 4 changes from "0" to "1", the superconducting Josephson junction element J of the superconducting Josephson switch G1 maintains the voltage state, so the information is "1". The state stored in is retained.

また、上述したように、情報が「０」で記憶さ
れている状態になつてから、電流路Ｈ３及びＨ５
に供給されている電流が「０」から「１」に転換
しても、超伝導ジヨセフソンスイツチＧ２の超伝
導ジヨセフソン接合素子Ｊが有電圧状態を保つて
いるので、情報が「０」で記憶されている状態が
保持されている。 Further, as described above, after the information is stored as "0", the current paths H3 and H5
Even if the current supplied to the switch changes from "0" to "1", the superconducting Josephson junction element J of the superconducting Josephson switch G2 maintains the voltage state, so the information remains "0". The stored state is retained.

さらに、電源線路Ｂに電流が供給されている状
態で、電流路Ｈ４及びＨ６に、２値表示で「１」
及び「０」をとる電流を「１」で供給した場合、
超伝導ジヨセフソンスイツチＧ３の制御線Ｃ１
に、その一端ａ２側から他端ａ１側に向つて電流
が流れていれば、すなわち、情報が「１」で記憶
されていれば、超伝導ジヨセフソンスイツチＧ３
の超伝導ジヨセフソン接合素子Ｊは零電圧状態か
ら有電圧状態に転換しないか、超伝導ジヨセフソ
ンスイツチＧ３の制御線Ｃ１に、その一端ａ１側
から他端ｓ２側に向つて電流が流れていれば、す
なわち、情報が「０」で記憶されているとすれ
ば、超伝導ジヨセフソンスイツチＧ３の超伝導ジ
ヨセフソン接合素子Ｊが零電圧状態から有電圧状
態に転換する。このため、電流路Ｈ６に供給され
た電流が、その電流路Ｈ６に流れている状態を保
つ。このことで、情報が「１」で読出される。 Furthermore, while current is being supplied to power supply line B, "1" is displayed on current paths H4 and H6 on a binary display.
When a current that takes "0" is supplied as "1",
Control line C1 of superconducting Josephson switch G3
If the current flows from one end a2 side to the other end a1 side, that is, if the information is stored as "1", the superconducting Josephson switch G3
Either the superconducting Josephson junction element J does not switch from the zero voltage state to the voltage state, or current flows through the control line C1 of the superconducting Josephson switch G3 from one end A1 to the other end S2. In other words, if the information is stored as "0", the superconducting Josephson junction element J of the superconducting Josephson switch G3 changes from the zero voltage state to the voltage applied state. Therefore, the current supplied to the current path H6 maintains a state in which it flows through the current path H6. With this, the information is read out as "1".

上述したように、第２図に示す本発明による超
伝導記憶回路の実施例によれば、電流路Ｈ３及び
Ｈ４に、２値表示で「１」及び「０」をとる電流
を「１」で供給することによつて、２値表示で
「１」及び「０」をとる情報を「１」で記憶する
ことができる。 As described above, according to the embodiment of the superconducting memory circuit according to the present invention shown in FIG. By supplying this information, information that takes "1" and "0" in binary display can be stored as "1".

また、電流路Ｈ３及びＨ５に、２値表示で
「１」及び「０」をとる電流を「１」で供給する
ことによつて、２値表示で「１」及び「０」をと
る情報を「０」で記憶することができる。 In addition, by supplying a current that takes "1" and "0" on a binary display as "1" to current paths H3 and H5, information that takes "1" and "0" on a binary display can be obtained. It can be stored as "0".

さらに、電源線路Ｂ及び電流路Ｈ６に、２値表
示で「１」及び「０」をとる電流を「１」で供給
した場合、電流路Ｈ６に供給された電流が、電流
路Ｈ６に流れている状態を保つことで、「０」で
記憶されている情報を、「１」で読出すことがで
きる。 Furthermore, if a current of "1" that takes "1" and "0" in binary display is supplied to power supply line B and current path H6, the current supplied to current path H6 will flow to current path H6. By maintaining this state, information stored as "0" can be read as "1".

また、電源線路Ｂ及び電流路Ｈ６に、２値表示
で「１」及び「０」をとる電流を「１」で供給し
た場合、電流路Ｈ６に供給された電流が、電流路
Ｈ６に流れなくなることで、「１」で記憶されて
いる情報を、「０」で読出すことができる。 In addition, when a current that takes "1" and "0" in binary display is supplied as "1" to power supply line B and current path H6, the current supplied to current path H6 will no longer flow to current path H6. By doing this, information stored as "1" can be read out as "0".

そして、この場合、電源線路Ｂ及び電流路Ｈ６
に供給する電流の順次は任意でよい。 In this case, the power line B and the current path H6
The order in which the currents are supplied may be arbitrary.

従つて、第２図に示す本発明による超伝導記憶
回路によれば、所要の電流路に順序を決めて電流
を供給する必要なしに、情報の記憶、及び読出し
をなし得るので、情報の記憶、及び読出しに用い
る電流を容易に得ることができ、また、情報の記
憶、及び読出しを第１図に示す従来の超伝導記憶
回路の場合に比し高速で行うことができるなどの
大なる特徴を有する。 Therefore, according to the superconducting memory circuit according to the present invention shown in FIG. 2, information can be stored and read without the need to supply current to required current paths in a determined order. , and the current used for readout can be easily obtained, and the storage and readout of information can be performed at higher speeds than in the case of the conventional superconducting memory circuit shown in Fig. 1. has.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、従来の超伝導記憶回路を示す接続図
である。第２図は、本発明による超伝導記憶回路
の実施例を示す接続図である。 Ｇ１〜Ｇ３……超伝導ジヨセフソンスイツチ、
Ｊ……超伝導ジヨセフソン接合素子、Ｃ１，Ｃ２
……制御線、Ｒ１，Ｒ２……抵抗、Ｂ……電源線
路、Ｈ３〜Ｈ６……電流路。 FIG. 1 is a connection diagram showing a conventional superconducting memory circuit. FIG. 2 is a connection diagram showing an embodiment of the superconducting memory circuit according to the present invention. G1~G3...Superconducting Josephson switch,
J...Superconducting Josephson junction element, C1, C2
...Control line, R1, R2...Resistor, B...Power supply line, H3-H6...Current path.

Claims (1)

【特許請求の範囲】 １ 超伝導ジヨセフソン接合素子と、少なくとも
２つの第１及び第２の制御線とを有し、上記超伝
導ジヨセフソン接合素子に２値表示で「１」及び
「０」をとる電流が「１」で供給されている状態
で、上記第１及び第２の制御線に２値表示で
「１」及び「０」をとる電流が「１」で供給され
た場合、上記超伝導ジヨセフソン接合素子が零電
圧状態から有電圧状態に転換する、第１、第２及
び第３の超伝導ジヨセフソンスイツチと、 第１及び第２の抵抗とを有し、 上記第１及び第２の超伝導ジヨセフソンスイツ
チの超伝導ジヨセフソン接合素子が直列に接続さ
れて第１の直列回路が形成され、 上記第１及び第２の抵抗が直列に接続されて第
２の直列回路が形成され、 上記第１及び第２の直列回路が並列に接続され
て並列回路が形成され、 該並列回路が電源線路に介挿され、 上記第３の超伝導ジヨセフソンスイツチの第１
の制御線の第１の端が、上記第１の直列回路の上
記超伝導ジヨセフソン接合素子の接続中点に、第
２の端が上記第２の直列回路の上記第１及び第２
の抵抗の接続中点に接続され、 上記第１及び第２の超伝導ジヨセフソンスイツ
チの第１の制御線が直列に接続されて第３の直列
回路が形成され、該第３の直列回路を含んで第３
の電流路が形成され、 上記第１及び第３の超伝導ジヨセフソンスイツ
チの第２の制御線が直列に接続されて第４の直列
回路が形成され、該第４の直列回路を含んで第４
の電流路が形成され、 上記第２の超伝導ジヨセフソンスイツチの第２
の制御線を含んで第５の電流路が形成され、 上記第３の超伝導ジヨセフソンスイツチの超伝
導ジヨセフソン接合素子を含んで第６の電流路が
形成され、 上記電源線路に電流が供給されている状態で、
上記第３及び第４の電流路に、２値表示で「１」
及び「０」をとる電流が、「１」で供給された場
合に、上記第３の超伝導ジヨセフソンスイツチの
第１の制御線に、２値表示で「１」及び「０」を
とる電流が、当該第３の超伝導ジヨセフソンスイ
ツチの第１の制御線の第２の端側から第１の端側
に流れることで、２値表示で「１」及び「０」を
とる情報が「１」（または「０」）で記憶され、 上記電源線路に電流が供給されている状態で、
上記第３及び第５の電流路に、２値表示で「１」
及び「０」をとる電流が「１」で供給された場合
に、上記第３の超伝導ジヨセフソンスイツチの第
１の制御線に、２値表示で「１」及び「０」をと
る電流が、当該第３の超伝導ジヨセフソンスイツ
チの第１の制御線の第１の端側から第２の端側に
向つて流れることで、２値表示で「１」及び
「０」をとる情報が「０」（または「１」）で記憶
され、 上記電源線路に電流が供給されている状態で、
上記第４及び第６の電流路に、２値表示で「１」
及び「０」をとる電流が、「１」で供給された場
合に、上記第６の電流路に供給された電流が、当
該第６の電流路に流れている状態を保つことで、
２値表示で「１」及び「０」をとる情報が「１」
（または「０」）で読出され、 上記電源線路に電流が供給されている状態で、
上記第４及び第６の電流路に、２値表示で「１」
及び「０」をとる電流が、「１」で供給された場
合に、上記第６の電流路に供給された電流が、当
該第６の電流路に流れなくなることで、２値表示
で「１」及び「０」をとる情報が「０」（または
「１」）で読出されることを特徴とする超伝導記憶
回路。[Claims] 1. A superconducting Josephson junction element and at least two first and second control lines, wherein the superconducting Josephson junction element takes "1" and "0" in binary representation. When a current of "1" is supplied to the first and second control lines with a binary value of "1" and "0" while the current is being supplied as "1", the superconductivity The Josephson junction element has first, second and third superconducting Josephson switches for switching from a zero voltage state to a voltage applied state, and first and second resistors; The superconducting Josephson junction elements of the superconducting Josephson switch are connected in series to form a first series circuit, and the first and second resistors are connected in series to form a second series circuit. , the first and second series circuits are connected in parallel to form a parallel circuit, the parallel circuit is inserted into the power supply line, and the first and second series circuits of the third superconducting Josephson switch are connected in parallel to form a parallel circuit;
A first end of the control line is connected to the connection midpoint of the superconducting Josephson junction element of the first series circuit, and a second end is connected to the connection midpoint of the superconducting Josephson junction element of the second series circuit.
connected to the connection midpoint of the resistors, the first control lines of the first and second superconducting Josephson switches are connected in series to form a third series circuit, and the third series circuit including the third
A current path is formed, and the second control lines of the first and third superconducting Josephson switches are connected in series to form a fourth series circuit, and the fourth series circuit includes the fourth series circuit. Fourth
A current path is formed, and the second current path of the second superconducting Josephson switch is formed.
A fifth current path is formed including the control line of the third superconducting Josephson switch, and a sixth current path is formed including the superconducting Josephson junction element of the third superconducting Josephson switch, and current is supplied to the power supply line. in a state where
“1” is displayed in binary on the third and fourth current paths above.
When the current that takes "0" and "1" is supplied, the first control line of the third superconducting Josephson switch takes "1" and "0" in binary display. When the current flows from the second end of the first control line of the third superconducting Josephson switch to the first end, information that takes "1" and "0" on a binary display is generated. is stored as “1” (or “0”), and current is being supplied to the above power line,
“1” is displayed in binary on the third and fifth current paths above.
When the current that takes "0" and "1" is supplied, the current that takes "1" and "0" in binary display is applied to the first control line of the third superconducting Josephson switch. flows from the first end side to the second end side of the first control line of the third superconducting Josephson switch, and takes "1" and "0" in the binary display. When the information is stored as "0" (or "1") and current is supplied to the above power line,
“1” is displayed in binary on the fourth and sixth current paths.
When the current that takes "0" is supplied as "1", the current supplied to the sixth current path is kept flowing in the sixth current path,
Information that takes “1” and “0” in binary display is “1”
(or "0"), and with current being supplied to the above power line,
“1” is displayed in binary on the fourth and sixth current paths.
When the current that takes "0" is supplied as "1", the current supplied to the sixth current path stops flowing through the sixth current path, and the current becomes "1" in the binary display. ” and “0” are read out as “0” (or “1”).
JP58148580A 1983-08-13 1983-08-13 Superconductive memory circuit Granted JPS6040594A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58148580A JPS6040594A (en) 1983-08-13 1983-08-13 Superconductive memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58148580A JPS6040594A (en) 1983-08-13 1983-08-13 Superconductive memory circuit

Publications (2)

Publication Number Publication Date
JPS6040594A JPS6040594A (en) 1985-03-02
JPH0120516B2 true JPH0120516B2 (en) 1989-04-17

Family

ID=15455916

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58148580A Granted JPS6040594A (en) 1983-08-13 1983-08-13 Superconductive memory circuit

Country Status (1)

Country Link
JP (1) JPS6040594A (en)

Also Published As

Publication number Publication date
JPS6040594A (en) 1985-03-02

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