JPH01206447A - Data processing system - Google Patents

Abstract

PURPOSE:To execute a data processing in a device which does not possess a ready signal input by stopping the supply of a master clock taking a processing timing when a data processing means receives data from the other circuit and a system proceeds to a subsequent processing. CONSTITUTION:When a data transfer request signal (2) is outputted from a data processing means 20a to a control means 20b, the control means 20 stops the master clock (4) which is supplied to the data processing means 20a, stops the action proceeding to the subsequent processing of the data processing means 20a, and outputs the data transfer request signal (2) to the other circuit, whereby it transfer data to the data processing means 20a. The control means 20b resets the supply of the master clock (4) which is supplied to the data processing means 20a and the data processing means 20a starts the various processing of data which have been received at the timing of the master clock (4).

Description

[Detailed Description of the Invention] [Summary] A device that does not have a ready signal input, regarding a data processing method that stops data processing operation while receiving data transfer from another circuit and puts data processing in a waiting state. The purpose is to realize a data processing method equipped with a hardware circuit to further simplify the control of data processing by using A data processing means which performs a predetermined process on the data and is not equipped with a control means for stopping the mask crotter that takes the data processing timing while the data is being received, and a data processing means that processes the data transferred from other circuits. and a control lower stage that controls the supply of the master clock necessary for the data processing means to proceed with the processing of the data, and the data processing means transfers the data to the data processing means via the control means. When receiving the transferred data from another circuit and proceeding to the next process, the amount control means for controlling the amount of data being transferred from another circuit stops supplying the mask blocker that takes the processing timing of the data processing means, and places the data processing means in a waiting state. Configure to control.

[Industrial application field]

The present invention relates to a data processing method that stops data processing operation while receiving data transfer from another circuit, and puts the data processing in a waiting state.

For example, in a character recognition device, a device for distance calculation is used to compare the distance between data read from a scanner and subjected to predetermined image processing and standard pattern data that is a dictionary of the image-processed data. It may be done.

Currently developed LSis for distance calculation generally do not have a ready signal necessary for interfacing with other functional blocks.

On the other hand, electronic devices such as character recognition devices generally tend to be more compact, and in order to satisfy such conditions, it is necessary to effectively use the LSi for distance calculation.

Note that the ready signal is used to create a waiting state so that the next process does not proceed until the process of another peripheral circuit is completed while it is operating.

[Conventional technology]

FIG. 5 shows a block diagram illustrating a conventional example.

The block diagram shown in FIG. 5 shows a part of the character recognition device, and its configuration is as follows: The distance between data read from a scanner (not shown) and subjected to predetermined image processing and various standard pattern data stored in advance A distance calculation circuit 1 that performs calculations, a central processing unit (hereinafter referred to as CPU) 2 that controls operations within the character recognition device based on software, and an image processing circuit 3 that performs predetermined image processing by reading from a scanner (not shown). , and a standard data memory 4 storing various standard pattern data.

Note that the distance calculation circuit 1 is configured with a device that does not have a ready signal input, and FIG. 5 shows the case where the distance calculation circuit 1 is used to process image processing data and various standard pattern data. A conventional example of distance calculation is shown below.

In this case, when the distance calculation command (2) is issued from the CPU 2 to the distance calculation circuit 1, the distance calculation circuit 1 issues image processing data transfer requests @, @' to the image processing circuit 3 via the CPU 2.

When the image processing circuit 3 completes the image processing of the comparison data, it returns a permission signal [phase] in response to the transfer request to the CPU 2, and the data transfer from the distance calculation circuit 1 and the image processing circuit 3 is performed under the control of the CPU 2. It will be done.

For the standard data memory 4, the predetermined standard image data is transferred to the distance calculation circuit 1 at the time when a permission signal in response to a data transfer request is issued from the distance calculation circuit 1.

In this state, the distance calculation circuit 1 performs distance calculations between the image processing data from the image processing circuit 3 and a plurality of standard pattern data under the control of the CPU 2, and finally calculates the distance. The result is distance calculation circuit 1
The data is then passed to the CPU 2, where character recognition is performed.

[Problem to be solved by the invention]

In the data processing method described above, the distance calculation process for character recognition is performed after the control of the CPU 2, which controls various processes based on software, so it takes time to communicate with the CPU 2, and the overall Processing becomes complicated.

In other words, since the number of accesses to CPU2 increases, C
There may be a lot of waiting time in the PU2 state, and there may be less time for CI) U2 to be occupied and control other processes.

Furthermore, each time one process is executed, CPU2
The processing becomes complicated.

An object of the present invention is to realize a data processing system including a hardware circuit for simplifying control of data processing using a device that does not require human power of a ready signal.

[Failure to solve the problem]

FIG. 1 shows a detailed diagram of the invention.

20a in the principle block diagram of the present invention shown in FIG. During data reception, the data processing means 20a is not equipped with a control means for stopping the master clock that takes the data processing timing, and 20b is the data processing means 20a that mediates the transfer data from other circuits. At the same time as the data processing means 20a transfers the data to the mask clock ■ necessary for processing the data
is a control means for controlling the supply of the data processing means 20.
When a receives data transferred from another circuit via the control means 201) and proceeds to the next process, the amount control means 20b that controls the amount of data transferred from the other circuit controls the data processing means 20a.
This problem is solved by configuring functional blocks to stop the supply of the master clock (2) that determines the processing timing and to control the data processing means 20b to a waiting state.

[For production]

When the data transfer request signal ■ is output from the data processing means 20a to the control means 20b, the control means 20b stops the mask clock ■ supplied to the data processing means 20a,
By stopping the operation of the data processing means 20a to proceed to the next process and at the same time outputting a transfer request signal (■) for the image-processed data to another circuit (not shown), the image-processed data is transmitted to the data processing means 20a. Have it transferred.

Control at this point? 11 means 20b is data processing means 20a
The data processing means 20a resumes the supply of the mask clock ■ supplied to the mask clock ■, and the data processing means 20a starts various processes such as a comparison process of the received image processing data with the standard pattern data and a distance calculation process at the timing of the mask clock ■. With this configuration, data processing can be performed using a simple processing procedure using a device that does not have a ready signal input.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 to 4.

FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining an embodiment of the control means in the present invention, and FIG. 4 is a diagram explaining the operating status of the control means in the present invention. . Note that the same reference numerals indicate the same objects throughout the figures.

The embodiment of the present invention shown in FIG. 2 has a CPU 2. Image processing circuit 3
．． A standard data memory 4, a distance calculation circuit 21 consisting of a distance calculation device without a ready signal input, and a distance calculation circuit 2.
The distance calculating section 20c includes a control circuit 22 that supplies a mask clock (1) to the mask clock (1) and controls data transfer.

Note that the distance calculation circuit 21 and control circuit 22 shown in FIG. 2 are the same as the data processing means 20a and control means 20 described in FIG.
FIG. 3 shows a specific example of the control circuit 22, which is an embodiment of FIG.

As explained in FIG. 5, the distance calculation circuit 21 performs image processing on data read by a scanner (not shown) in the image processing circuit 3, and converts the data into +4i +4i- pattern data stored in the standard data memory 4 and the image. This is used in a character recognition device that recognizes data image-processed by the CPU 2 by calculating the distance from the processed data and sending the calculation result to the CPU 2.

When the distance calculation circuit 21 requests the image processing circuit 3 to transfer data, it sends a data transfer request signal (■) to the image processing circuit 3 via the control circuit 22.

When the control circuit 22 receives the data transfer request signal (2) from the distance calculation circuit 21, it stops sending out the mask clock (2) that is being supplied to the distance calculation circuit 21.

The mask clock (2) supplied to the distance calculation circuit 21 is created by a signal generated from an oscillator (O3C) 228 within the control circuit 22.

Note that the control circuit 22 has a configuration as shown in FIG. That is, inverter circuits 221 and 223, NOR circuits 222 and 224, and flip-flop circuits (hereinafter referred to as F and F)
circuits) 225 to 227, and the above-mentioned oscillator (O3
C) It consists of 228.

Further, a time chart showing the operation of this control circuit 22 is shown in FIG.

The signal generated from the oscillator (O3C) 22B is a clock ■ having a predetermined speed as shown in FIG. Generated by NOR condition with positive output.

When the data transfer request signal ■ is sent from the distance calculation circuit 21 to the control circuit 22, the inverter circuit 221-
F, F circuit 2 at F, F circuit 225-NOR circuit 222
The positive output of 26 is inverted to a state in which the clock ■ is inhibited, and the supply of the master clock ■ to the distance calculation circuit 21 is stopped.

On the other hand, the data transfer request signal (2) is sent to the image processing circuit 3 in parallel. When the image processing circuit 3 completes the image processing of the data to be transferred, it sends a request permission signal (2) to the control circuit 22.

The positive output of the F, F circuit 227 that receives this inverts the positive output of the F, F circuit 226 from the state where it suppresses the clock ■, and the clock ■ via the NOR circuit 224 is sent to the distance calculation circuit 21 as the master clock ■. supply will be resumed.

Further, the distance calculation circuit 21 takes in the image processing data through a path not shown, and performs distance calculations with respect to a plurality of standard pattern data stored in the standard data memory 4.
The calculation result is sent to the CPU 2, and the image-processed data is recognized by the CPU 2.

FIG. 4 shows the processing time chart 1 of the control circuit 22. When the data transfer request signal ■ is received, the transmission of the mask clock ■ is stopped, and when the request permission signal ■ is received, the transmission of the mask clock ■ is stopped. Sending is resumed. This period is the blocking period (8) of the mask clock (2).

By performing the image processing data recognition process in the above-described manner, the number of accesses to the CPU 2 is significantly reduced, and the image processing data recognition process can be realized in a simple manner through a dedicated hardware circuit.

〔Effect of the invention〕

According to the present invention as described above, data processing performed by a device that does not have a ready signal input can be realized in a simple manner.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining an embodiment of the control means in the present invention, and FIG. 4 is a block diagram explaining the present invention in detail. FIG. 5 is a diagram illustrating the operating status of the control means in the invention, and FIG. 5 is a block diagram illustrating a conventional example. In the figure, 21 is a distance calculation circuit, 2 is a CPU, 3 is an image processing circuit, 4 is a standard data memory, 20a is a data processing means, 20b is a control means, 20c is a distance calculation unit,
22 is a control circuit, 221 and 223 are inverter circuits, 222 and 224 are NOR circuits, 225 to 227 are F and F circuits, and 228 is an oscillator (O3C). ,−−−−,,,,,−−−,−,,,,,,,,,,,,
,,,,---,,,,,,,,,,,,,,,,,,,
, , , - , , - (,,20 Detailed block diagram explaining the present invention Figure 1 Block diagram explaining the 'JUM sequence of the present invention Figure 2 Tree full-E middle-b1 11. Misaki Zisa J. I1 Works 4 Yuki, 6
Store Showa 73rd Ward (Fig. 4 Bronc diagram explaining sub-H column)

Claims (1)

[Claims] Transfer data from other circuits to a data transfer request permission signal (
[3]), and performs predetermined processing on the received data, and controls to stop the master clock ([4]) that takes data processing timing while receiving the data. Data processing means (
20a), and the master clock (20a) necessary for transferring the transfer data from the other circuit to the data processing means (20a) and for the data processing means (20a) to proceed with processing the data. [4] Control means (
20b), when the data processing means (20a) receives the transfer data from the other circuit via the control means (20b) and proceeds to the next process, the data from the other circuit is transferred. While the control means (20b) is
A data processing method characterized in that the supply of a master clock ([4]) that determines the processing timing of the data processing means (20a) is stopped, and the data processing means (20a) is controlled to be in a waiting state.