JPH0431423B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A buffer address management method for a device that performs data communication processing and data processing using a multiprocessor, in which a first processor performs data buffer processing between two processors. (subprocessor) calculates and obtains the DMA address necessary for direct access transfer (hereinafter referred to as DMA transfer) from the physical address of the buffer notified by the second processor (main processor), and always manages both as a pair. This makes it possible to reduce the overhead calculation time of buffering processing due to differences in main addressing methods.

[Industrial application field]

The present invention relates to a device that processes data exchange between a processor that performs data communication processing and a processor that performs data processing, and particularly relates to a buffer address management method for a multiprocessor that has a plurality of addressing methods.

For example, a communication control device in an online computing system functions as a type of input/output control device, accommodates communication lines corresponding to multiple input/output devices, and is a processor (hereinafter referred to as a subprocessor) that controls the communication system. It is controlled by a multiprocessor having a function and a processor (hereinafter referred to as main processor) function for processing data exchanged between the host device and the communication line.

When looking at the communication system of such a communication control device from the perspective of input/output control, (1) the data transfer speed on the communication line is extremely slow compared to the internal processing speed of the host device.

(2) Data transfer on the communication line is performed asynchronously with the internal processing of the host device.

(3) The number of communication lines, that is, the number of input/output terminals is large.

It has the following characteristics.

Therefore, in order to smoothly and efficiently process data exchange between one host device and a large number of terminals connected via multiple communication lines, it is necessary to convert and match the speed by buffering the exchanged data. becomes.

However, the buffer addressing methods used by the sub-processor that normally controls the communication system and the main processor that processes data are different, and a large amount of processing time is required for address conversion during buffering processing of data to be sent and received. Since overhead calculation time is required, it is hoped that a buffer address management system that efficiently performs such processing will be put into practical use.

[Conventional technology]

FIG. 4 is a block diagram for explaining the conventional example, and FIG. 5 is a diagram for explaining the processing procedure of the conventional example.

FIG. 4 is a block diagram showing an outline of the configuration of the communication control device 10. This communication control device 10 accommodates a plurality of communication lines #0 to #n, and controls and communicates these communication lines #0 to #n. Subprocessor 2 that performs the interface function with lines #0 to #n
0 and communication line #0 to the storage unit 32 under management.
A main processor 30 that controls buffering processing of data exchanged via ~#n and data exchange processing with a host device (not shown), and a sub-processor 20 to main processor 30.
The DMA circuit 40 has a function of processing data transfer to the internal storage section 32 using DMA.

Further, the sub-processor 20 includes a processing section 21 that executes communication system control processing operations based on a control program.
, an address memory 24 that stores the physical address sent from the main processor 30 to the storage unit 32, an address conversion unit 22a that converts the physical address into an address for DMA processing, and
The address converter 22b converts a DMA address into a physical address.

Note that the conversion performed by the address conversion units 22a and 22b is, for example, a 16-bit system (main processor 30).
This means converting an address for processing into an 8-bit system (subprocessor 20).

Next, for example, when data is transferred from the communication line #i to the host device (not shown), it is buffered once to the storage section 32 in the main processor 30 in order to adjust for differences in data processing speed. and sends it to a host device (not shown).

At this time, the main processor 30 notifies the sub-processor 20 of the physical address for buffering to the storage section 32, and temporarily stores the physical address in the address memory 24.

The physical address is converted into the address by the address converter 22a.
It converts it into a DMA address and sends it to the DMA circuit 40, accesses the DMA circuit 40, and directly accesses the storage unit 32 via the DMA circuit 40 to buffer the data from the communication line #i.

Note that the address converted into a DMA address is converted again from a DMA address to a physical address' by the address conversion unit 22b, and then sent to the main processor 3.
0 to notify the storage unit 32 of data buffering.

This process is repeated for multiple physical addresses. Incidentally, this processing procedure will be explained with reference to FIG.

That is, the main processor 30 supplies the receiving buffer (corresponding to the storage section 32) to the sub-processor 20 as a physical address, repeats this until the buffer supply is finished, and stores the physical address in the address memory 24. (Step 100,
101) The sub-processor 20 takes out one of the reception buffers, that is, one of the physical addresses, and sends it to the address conversion unit 2.
2a converts the address to a DMA address,
Set in the register in the DMA circuit 40. (Step 102) When the data reception to the register in the DMA circuit 40 and the DMA transfer to the corresponding receiving buffer are completed, the corresponding DMA address is converted into a physical address ' by the address conversion section 22b, and buffering to the corresponding receiving buffer is completed. Notify.

Next, the next reception buffer, ie, one physical address, is extracted and the same process is repeated. (Steps 103 and 104) [Problems to be solved by the invention] In the buffer address management method described above,
Every time data is set in the register in the DMA circuit 40, address conversion from a physical address to a DMA address is repeatedly performed.

In addition, each time the main processor 30 is notified of data buffering, address conversion from a DMA address to a physical address is performed, which increases the overhead calculation time, and therefore increases the processing time for data exchange. The point was hot.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the principle of the invention. The principle block diagram shown in FIG. 1 accommodates a plurality of communication lines #0 to #n, and a first processor (sub-processor) that mainly controls communication processing through these plurality of communication lines #0 to #n. ) 20, a physical address of the storage unit 32 managed by the second processor (main processor) 30, and a direct access circuit 40 obtained by converting the address from the physical address to directly access the storage unit 32. an address memory 23 that manages and stores addresses as a pair, a second processor (main processor) 30 that mainly controls data processing transmitted and received via each communication line #0 to #n, and each communication line A storage unit 32 that buffers data sent and received via each communication line #0 to #n to a buffer corresponding to a physical address, and a DMA that buffers data sent and received via each communication line #0 to #n to the storage unit 32. The DMA circuit 40 performs buffering.

[Effect]

Data sent and received by the host device via the communication system is transferred to the data buffer (storage unit) in the main processor through the sub-processor that manages the communication system.
When performing buffering processing using DMA transfer, the physical address of the data buffer (storage unit) sent from the main processor is converted into an address converter.
The physical address is converted into a DMA address, and the physical address and the converted DMA address are stored and managed as a pair in the address memory within the subprocessor.

Next, the DMA address and the corresponding physical address are read from the address memory, and address conversion is performed by configuring to notify the DMA processing to the data buffer (storage unit) and the buffering processing to the data buffer (storage unit). This makes it possible to prevent an increase in processing time due to overhead.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating an embodiment of the present invention, and FIG. 3 is a diagram illustrating a processing procedure in the embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

When the address conversion unit 22 of the sub-processor 20 in this embodiment receives the physical address corresponding to the reception buffer notified from the main processor 30, it immediately calculates the DMA address and converts the physical address and the calculated DMA address. They are sent as a pair to the address memory 23.

Address memory 2 that received this pair of addresses
3 is stored under the control of the processing unit 21, and is subsequently managed as a pair of addresses. (Steps in Figure 3)
Equivalent to 100, 105. (Similarly below) When the main processor 30 has finished supplying the receive buffer (physical address) and is ready to receive data, the relevant register is stored in the DMA circuit 40.
The DMA address is read and set, and data can be received into the reception buffer (storage unit 32).
(Steps 101 and 106) When the data transfer of the received data to the reception buffer (storage unit 32) is completed, the sub-processor 20 reads the physical address ', sends this physical address ' to the main processor 30, and transfers the data. Notify of receipt.

In this way, since the addresses of a plurality of reception buffers (storage unit 32) are managed in advance by pairing a physical address and a corresponding DMA address, the overhead calculation time of processing due to address conversion during data transfer is reduced. data reception processing time becomes faster.

〔Effect of the invention〕

According to the present invention as described above, an increase in processing time due to overhead calculations during address conversion is prevented, and data reception processing speed is improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the principle of the present invention.
FIG. 2 is a block diagram explaining an embodiment of the present invention;
FIG. 3 is a diagram explaining the processing procedure in the embodiment of the present invention, FIG. 4 is a block diagram explaining the conventional example,
FIG. 5 shows diagrams explaining the processing procedure of the conventional example. In the figure, 10 is a communication control device, 20 is a sub-processor, 21, 31 are processing units, 22, 22
Reference numerals a and 22b designate address conversion units, 23 and 24 address memories, 30 a main processor, 32 a storage unit, and 40 a DMA circuit, respectively.

Claims (1)

[Claims] 1. Accommodates a plurality of communication lines #0 to #n,
It has a first processor 20 that controls communication processing through these plurality of communication lines #0 to #n, and a second processor 30 that controls data processing that is sent and received through each of the communication lines #0 to #n. The data sent and received through each of the communication lines #0 to #n is stored in the storage unit 32 in the second processor 30.
In a device that directly accesses and stores data via a direct access circuit 40, the storage section 32 managed by the second processor 30 is accessed through each of the communication lines #0 to #n managed by the first processor 20. When buffering the transmitted and received data processing via the direct access circuit 40, an address conversion means converts the physical address of the buffer sent when the storage unit 32 is controlled by the second processor 30 and the physical address. The buffer is characterized in that the direct access address obtained by the direct access circuit 40 for directly accessing the storage unit 32 is stored in a pair in the memory 23 in the first processor 20 and managed. Address management method.