JPH01207676A - Inspecting method for semiconductor integrated circuit element - Google Patents
Inspecting method for semiconductor integrated circuit elementInfo
- Publication number
- JPH01207676A JPH01207676A JP63032260A JP3226088A JPH01207676A JP H01207676 A JPH01207676 A JP H01207676A JP 63032260 A JP63032260 A JP 63032260A JP 3226088 A JP3226088 A JP 3226088A JP H01207676 A JPH01207676 A JP H01207676A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- input
- input signal
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 8
- 238000005259 measurement Methods 0.000 claims abstract description 15
- 238000007689 inspection Methods 0.000 claims abstract description 10
- 238000012360 testing method Methods 0.000 claims description 46
- 238000010586 diagram Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体集積回路素子の検査方法に関する。[Detailed description of the invention] Industrial applications The present invention relates to a method for testing semiconductor integrated circuit devices.
従来の技術
近年、半導体集積回路素子は高集積化、高機能化し、そ
の検査結果もますまず高い検査精度が必要となっている
。以下に従来の半導体集積回路素子の特性検査方法につ
いて説明する。BACKGROUND OF THE INVENTION In recent years, semiconductor integrated circuit devices have become highly integrated and highly functional, and their test results require increasingly high test accuracy. A conventional method for testing characteristics of semiconductor integrated circuit elements will be described below.
第２図は従来の半導体集積回路素子の特性検査方法を説
明するための系統ブロック図である。第２図において、
１は特性検査装置、２は信号源、３は供試半導体集積回
路素子、４は入力信号供給用ケーブル、５は周辺回路リ
レー、及びバッファアンプ等を実装しているテストボー
ド、６は入力信号側リレー、７は出力信号側リレー、８
は出力信号供給用ケーブル、９は出力信号の測定系であ
る。FIG. 2 is a system block diagram for explaining a conventional characteristic testing method for semiconductor integrated circuit elements. In Figure 2,
1 is a characteristic testing device, 2 is a signal source, 3 is a semiconductor integrated circuit device under test, 4 is an input signal supply cable, 5 is a test board on which peripheral circuit relays, buffer amplifiers, etc. are mounted, and 6 is an input signal side relay, 7 is output signal side relay, 8
9 is an output signal supply cable, and 9 is an output signal measurement system.
以上のように構成された半導体集積回路素子の特性検査
系による測定方法について説明する。入力検査条件にも
とづいて入力信号源２で所定信号が作られ、その入力信
号が、ケーブル４．リレー６を介して供試半導体集積回
路素子３に加えられる。そして、供試半導体集積回路素
子３よりの出力信号がリレー７、及びケーブル８を介し
て、出力信号の測定系９に加えられる。この出力信号の
測定系９での測定結果は、特性検査装置１内のｃｐｕ部
分で、出力検査条件に基づいて判定される。A measurement method using the characteristic testing system for semiconductor integrated circuit elements configured as described above will be explained. A predetermined signal is generated by the input signal source 2 based on the input test conditions, and the input signal is transmitted to the cable 4. It is applied to the semiconductor integrated circuit device under test 3 via the relay 6 . Then, the output signal from the semiconductor integrated circuit element 3 under test is applied to an output signal measurement system 9 via a relay 7 and a cable 8. The measurement result of this output signal in the measurement system 9 is determined by the CPU section in the characteristic testing device 1 based on the output testing conditions.
発明が解決しようとする課頴
しかしながら、上記の従来例では入力信号のばらつきケ
ーブル、およびリレー等の実装部分でのロスが無視でき
ない程大きくなり、検査装置から発せられる入力信号が
検査条件通りの入力信号レベルで供試半導体集積回路素
子３に加わらなくなる。その結果、供試半導体集積回路
素子３からの出力も正常でな（なり、正しい検査ができ
なくな−るという欠点を有していた。Problems to be Solved by the Invention However, in the conventional example described above, variations in input signals occur.Loss in cables and mounting parts such as relays becomes so large that it cannot be ignored. The signal level is no longer applied to the semiconductor integrated circuit element 3 under test. As a result, the output from the semiconductor integrated circuit device 3 under test is also not normal, resulting in a drawback that correct testing cannot be performed.
本発明は上記従来例の問題点を解決するもので１、供試
半導体集積回路素子の入力に入力検査条件通りの信号を
加えることにより、正しい検査ができるようにした半導
体集積回路素子の特性検査方法を提供する事を目的とし
ている。The present invention solves the above-mentioned problems of the prior art. 1. Characteristic testing of semiconductor integrated circuit elements that enables correct testing by applying a signal that meets the input testing conditions to the input of the semiconductor integrated circuit element under test. The purpose is to provide a method.
課題を解決するための手段
本発明の半導体集積回路素子の検査方法は、予め、出力
信号を測定する測定系により実際に供試半導体集積回路
素子に加わる入力信号を、その入力信号レベルを所定の
指定条件に合致させる調整を行う過程をそなえたもので
ある。Means for Solving the Problems In the semiconductor integrated circuit device testing method of the present invention, an input signal actually applied to a semiconductor integrated circuit device under test is measured in advance by a measurement system for measuring an output signal, and the input signal level is adjusted to a predetermined level. It has a process of making adjustments to meet specified conditions.
作用
この構成によって、供試半導体集積回路素子の実際の入
力信号が測定でき、その測定値に基づき、入力信号源を
調整することにより、指定の入力検査条件通りの入力信
号を供試半導体集積回路素子に印加できる。Function: With this configuration, the actual input signal of the semiconductor integrated circuit device under test can be measured, and by adjusting the input signal source based on the measured value, the input signal that meets the specified input test conditions can be measured on the semiconductor integrated circuit device under test. It can be applied to the element.
実施例
以下、本発明を、実施例により、図面を参照しながら説
明する。第１図は本発明の一実施例の半導体集積回路素
子の特性検査方法を説明するための系統ブロック図であ
る。第１図中の符号１〜９で表した各構成体は第２図と
全く同じであり、これに、入力信号を直接、出カケープ
ル８に供給するためのリレー１０が分岐結合されている
。最初、リレー６をオン、リレー１０をオン、リレー７
をオフにする。次に供試半導体集積回路素子３を検査条
件通りの状態にする。この状態では、入力信号がリレー
１０、ケーブル８を通り、測定系９で測定される。EXAMPLES Hereinafter, the present invention will be explained by way of examples with reference to the drawings. FIG. 1 is a system block diagram for explaining a method for testing characteristics of a semiconductor integrated circuit device according to an embodiment of the present invention. 1 to 9 are exactly the same as in FIG. 2, and a relay 10 for directly supplying an input signal to the output cable 8 is branch-coupled thereto. First, turn on relay 6, turn on relay 10, turn on relay 7
Turn off. Next, the semiconductor integrated circuit device 3 under test is brought into a state that meets the test conditions. In this state, the input signal passes through the relay 10 and the cable 8 and is measured by the measurement system 9.
その測定結果に基づき、入力信号源２を調整して、その
信号が供試半導体集積回路素子３の所定入力検査条件に
なるようにする。そして、この入力検査条件通りの信号
をリレー１０をオフ、リレー７をオンにして、供試半導
体集積回路素子３の出力信号を測定系９で測定し判定す
る。Based on the measurement results, the input signal source 2 is adjusted so that the signal meets the predetermined input test conditions for the semiconductor integrated circuit device 3 under test. Then, the relay 10 is turned off, the relay 7 is turned on, and the output signal of the semiconductor integrated circuit element 3 under test is measured by the measurement system 9 to determine the signal that meets the input test conditions.
発明の効果
本発明によれば、供試半導体集積回路素子の実際の検査
状態に於ける入力信号を、予め、その出力信号測定系で
監視する過程をそなえたことにより、常に、検査条件に
合致した入力信号により検査ができる。更に同一仕様の
別の検査装置や別のテストボードでテストしても入力信
号系のばらつきは全て吸収できるため、相関のとれた信
頼性の高い検査を行うことができる。Effects of the Invention According to the present invention, by providing a process in which the input signal in the actual test state of the semiconductor integrated circuit device under test is monitored by the output signal measurement system in advance, the test condition is always met. Inspection can be performed using the input signal. Furthermore, even if a test is performed using a different test device or a different test board with the same specifications, all variations in the input signal system can be absorbed, so that highly correlated and highly reliable tests can be performed.
第１図は本発明実施例を説明するための系統ブロック図
、第２図は従来例を説明するための系統ブロック図であ
る。
１・・・・・・特性検査装置、２・・・・・・入力信号
源、３・・・・・・供試半導体集積回路素子、４・・・
・・・入力信号供給用ケーブル、５・・・・・・テスト
ボード、６．７．１０・・・・・・リレー、８・・・・
・・出力信号供給用ケーブル、９・・・・・・出力測定
系。
代理人の氏名 弁理士 中尾敏男 はか１名こ３−一−
イ共試手導イ本づ−［ｒａ αｔ３ミｊ市Ｑミター第２
図FIG. 1 is a system block diagram for explaining an embodiment of the present invention, and FIG. 2 is a system block diagram for explaining a conventional example. DESCRIPTION OF SYMBOLS 1...Characteristics testing device, 2...Input signal source, 3...Semiconductor integrated circuit element under test, 4...
...Input signal supply cable, 5...Test board, 6.7.10...Relay, 8...
...Output signal supply cable, 9...Output measurement system. Name of agent: Patent attorney Toshio Nakao
A joint exam guide I book [ra αt3 mij city Q miter 2nd]
figure
Claims (1)
る検査測定系を用いて、予め、入力信号を、直接、前記
出力信号測定系で、測定検査し、入力信号源を所定の入
力指定条件に合致させる調整を行ったのち、その入力信
号を前記供試半導体集積回路素子に入力することを特徴
とする半導体集積回路素子の検査方法。Using an inspection and measurement system that measures the output signal electrical characteristics of the semiconductor integrated circuit device under test, the input signal is directly measured and inspected in advance with the output signal measurement system, and the input signal source is adjusted to predetermined input specified conditions. 1. A method for testing a semiconductor integrated circuit device, characterized in that, after making adjustments to match, the input signal is input to the semiconductor integrated circuit device under test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63032260A JPH01207676A (en) | 1988-02-15 | 1988-02-15 | Inspecting method for semiconductor integrated circuit element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63032260A JPH01207676A (en) | 1988-02-15 | 1988-02-15 | Inspecting method for semiconductor integrated circuit element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01207676A true JPH01207676A (en) | 1989-08-21 |
Family
ID=12354041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63032260A Pending JPH01207676A (en) | 1988-02-15 | 1988-02-15 | Inspecting method for semiconductor integrated circuit element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01207676A (en) |
-
1988
- 1988-02-15 JP JP63032260A patent/JPH01207676A/en active Pending
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