JPH01220194A - block address generator - Google Patents

Abstract

PURPOSE:To obtain a block address for reproducing by comparing a forecasting block address with a synthesizing block address based on a reproducing block address by a revolving head and outputting the synthesizing block address when an error is smaller than a prescribed value. CONSTITUTION:The block address of 7 bits, which is reproduced by the revolving head and latched by a block address latching circuit 4, and the block address of 8 bits are synthesized by the outputs of a synchronizing signal detecting circuit 3 and a block address counter circuit 6 in a synthesizing block address generating circuit 13. On the other hand, in a reference block address circuit 11 of a forecasting means to be controlled by a revolving head switch pulse signal, the forecasting block address of the 8 bits is formed and compared with the synthesizing block address. When the error is smaller than the prescribed value, the circuit 6 is controlled through an AND circuit 7 and the synthesizing block address of the 8 bits is outputted. Accordingly, from the reproducing block address of the 7 bits for flag, etc., the block address is formed to be used for the reproducing of the 8 bits as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a block address generation device for recording and reproducing serial digital data.

2. Description of the Related Art Recording and reproducing of serial digital data has been widely used in many fields, and a recent example is the digital audio tape recorder (I) AT).

As an example, if we consider a rotary head type digital audio tape recorder (R-DAT), its recording signal is serial digital data, Do
A synchronization signal 5YNC of a specific pattern is inserted into the block period B, which is equally spaced in time, for the , , and Dn, and in addition, a code ID (Identification) for identifying the contents recorded in the serial digital data, etc., and a block Address code B A (B, 1ock
address), and an error detection code EDC (Error Detection Code) for ID and BA.
Code). Each code is composed of 8 pins and 7 pins, and is called a symbol.

FIG. 3 shows a block diagram of a conventional block address generator. In FIG. 3, serial digital data during reproduction is inputted from an input terminal 2, a synchronizing signal is detected in a synchronizing signal detection circuit 3, and a signal phase-synchronized with the synchronizing signal is created. The serial digital data is converted into an address code B by a latch pulse from the synchronization signal detection circuit 3 in the block address latch circuit 4.
A is latched. Furthermore, the serial type digital data is passed to the parity check circuit 6 by the pulse from the synchronization signal detection circuit 3. For example, in the code structure shown in FIG. ) Determine whether the parity is correct, expressed as even or odd parity. The output of the synchronization signal detection circuit 3 is input to the clock terminal of the block address counter circuit 6, and is also input to the rotating head (not shown) via the input terminal 1.
A head switch pulse signal indicating the rotational position of the head 1 switch pulse signal is input to the reset terminal of the block address counter circuit 6, and the contents of the counter of the block address counter circuit 6 are reset at the edge of the head 1 switch pulse signal,
Since then, it has been counted up using the 100th issue of the same period as a clock.
It is reset at the edge of the next head switch pulse signal, and this process is repeated thereafter. The output (8 bits) of the block address counter circuit 6 and the output (8 bits) of the block address latch circuit 4 are input to the block address mismatch circuit 8, which determines whether the block address values are the same. The output and the output of the parity check circuit 6 are input to the ND circuit 7, and if the parity check result is correct and the block address values do not match, a pulse is generated from the A r4D circuit 7 and the block address counter circuit 6 is loaded. The output (8 bits) of the block address latch circuit 4 is input to the data input terminal of the block address counter circuit 6, and the address value of the block address latch circuit 4 is loaded into the block address counter circuit 6. The output (8 bits) of the block address counter circuit 6 is outputted via the output terminal 9, and is used as the RA of the reproduced digital data.
M (Random Access Memory)
It forms part of the address value when writing to.

By the way, in a magnetic recording and reproducing apparatus that records and reproduces video signals on a magnetic tape using a rotating head.

When recording and reproducing an audio signal as a digital signal, the analog audio signal is converted to a sampling frequency f, (e.g. f
, = 48 k)h), the field frequency fv (NTSC system f
v=E59.94Hz) is 800.8,
Therefore, the number of data in the field is set to two types (large and small) (for example, near 92 and 810), and the field with less audio data (
792 data field), dummy data is added and recorded as a shortage.

Since the information indicating whether the dummy data is added or not is recorded using the MSB of the address code BA in Figure 2, the block address value is recorded in 7 bits.For example, if the number of blocks in one field is 136, It is recorded on the magnetic tape in the following state (0-127° 0-e).

Problem to be Solved by the Invention However, when digitally recording an audio signal in synchronization with a video signal as described above, the block address recorded on the magnetic tape is only 7 bits, so the block address value at the time of playback is (8 bits) cannot be created directly from the recording block address value (7 pintos).

The present invention has been made in view of the above-mentioned problems, and provides a block address generation device that generates block address values when recording and reproducing digitized audio signals as well as video signals.

Means for Solving the Problems In order to achieve the above object, the block address generation device of the present invention includes block address prediction means for predicting an address recorded at a playback position according to the rotational position of a rotary head, and a rotary head. a composite address value generating means for creating a composite address value from a playback address value read from the magnetic tape and an output address value; and an address value comparison for comparing the composite address value and the predicted address value by the block address predicting means. The present invention is characterized in that it includes means and selection means for selecting the composite address value as a new output address value only when the comparison error by the address value comparison means is within a predetermined range.

The present invention has the above-described configuration, and is used to reproduce a magnetic tape on which a digital signal to which a synchronization pattern and an address have been added is recorded using a rotary head so that the synchronization pattern and address are at a predetermined position on the track. , detect the rotational position of the rotary head that performs playback, predict the recorded address (8 bits) from the detected rotational position, and calculate the playback address value (7 bits) and output address value (upper 1 bit). Synthesized address value (8 bits) from
The synthesized address value (8 bits) is compared with the predicted address value (8 bits), and if the comparison error is within a predetermined range, the synthesized address value (8 bits) is adopted as the new output address value. Therefore, a correct address value is created, and the write operation of reproduced digital data to the RAM can be performed correctly.

EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the block address generation device of the present invention.

In FIG. 1, serial digital data at the time of reproduction is input through an input terminal 2, a synchronizing signal is detected in a synchronizing signal detection circuit 3, and a signal whose phase is synchronized with the synchronizing signal is created. The serial type digital data is sent to the synchronization signal detection circuit 3 in the block address latch circuit 4.
Address code BA is latched by a latch pulse from .

Further, the serial type digital data is processed by the parity check circuit 5 by the pulse from the synchronization signal detection circuit 3.
For example, in the code structure shown in FIG. 2, it is determined whether the parity is correct to even or odd parity as expressed by P=W1*W2 or P=W1*W2 (* indicates exclusive OR). The output of the synchronization signal detection circuit 3 is input to the clock terminal of the block address counter circuit 6, and is also input to the rotating head (not shown) via the input terminal 1.
A head switch pulse signal indicating the rotational position of the block address counter circuit 6 is input to the reset terminal of the block address counter circuit 6, and the contents of the counter of the block address counter circuit 6 are reset at the edge of the head switch pulse signal, and from then on, the counter is counted using the synchronization signal as a clock. It is then reset at the edge of the next head switch pulse signal, and is repeated thereafter. The output of the block address counter circuit 6 (lower 7 bits) and the output of the block address latch circuit 4 (lower 7 bits) are input to a block address mismatch circuit 8, which determines whether the block address values are the same. Output of block address latch circuit 4 (
The lower 7 bits) and the output (upper 1 bit) of the block address counter circuit 6 are input to the composite block address generation circuit 13, and the most significant bit of the block address is clocked by the output of the block address counter circuit 6, and the lower 7 bits are clocked. A composite block address value consisting of the output of the address latch child circuit 4 is created.

Furthermore, the head switch pulse signal from the input terminal 1 is input to the reference block address generation circuit 11, and the reference block address generation circuit 11 is composed of a counter circuit.
The counter circuit is reset at the edge of the head switch pulse signal, counts up based on the reference clock, and the counter circuit is reset at the edge of the next head switch pulse signal, generating a block address value corresponding to the position of the rotating head of the magnetic tape. . The output (8 bits) of the reference block address generation circuit 11 and the output (8 bits) of the composite block address generation circuit 13 are input to the address value comparison circuit 12. Here, if the predicted address value NA of the reference block address generation circuit 11 and the composite address value NB of the composite block address generation circuit 13 are assumed, then the address value comparison circuit 12 performs the operation N = l NA to obtain the absolute value of the difference shown below. -NBl, and determines whether the calculation result N is larger or smaller than a predetermined value NREF. The output of the parity check circuit 5, the output of the block address mismatch circuit 8, and the output of the address value comparison circuit 12 are A
If the parity check result is correct, the block address values do not match, and NREF>lNA-NBl holds true, the AND circuit 7 generates a pulse.

It is input to the load terminal of the block address counter circuit 6. The output (8 bits) of the composite block address generation circuit 13 is input to the data input terminal of the block address counter circuit 6, and is loaded into the block address counter circuit 6 by the load pulse from the AND circuit 7. The output (8 bits) of the block address counter circuit 6 is outputted via the output terminal 9, and is used as the R of the reproduced digital data.
It forms part of the address value when writing to AM.

Effects of the Invention As described above, according to the present invention, by limiting the range of block address values using address values predicted from the rotational position of the rotary head, the most significant bit of the block address value is created, and the correct block address value is generated. The reproduced digital data can be written to the RAM. Furthermore, even if the parity check circuit mistakenly determines that the block address value is correct, the range in which the reproduced digital data is written to the RAM is limited to the vicinity of the predicted address value. Even if one track is not completely written to the RAM, it is possible to start error correction processing for the reproduced digital data written to the RAM, and the time from when the reproduced digital data is written to the RAM until the start of error correction is long. It can be shortened to width. Therefore, the data processing time required for digital recording and reproduction of audio signals can be greatly reduced. Therefore, when recording and reproducing a video signal and an audio signal, there is an advantage that the processing delay time difference (TD) of the audio signal can be made smaller than that of the video signal. In particular, even if the number of dubbings (n: number of times) increases, the processing delay time difference (Tp) of the audio signal with respect to the video signal is
Since n=n×Tp) is also small, there is an advantage that the viewer does not notice the difference in processing delay time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a block address generator according to an embodiment of the present invention, FIG. 2 is a signal configuration diagram of serial digital data applied to input terminal 2 in FIG. 1, and FIG.
The figure is a block diagram of a conventional block address generator. 1.2...Input terminal, 3...Synchronization signal detection circuit, 4...Block address latch circuit, 6...Parity check circuit, 6... ...Block address counter circuit, 7...A N
D circuit, 8...Block address mismatch circuit,
9...Output terminal, 11...Reference block address generation circuit, 12...Address value comparison circuit, 13...Composition block address generation circuit.

Claims (1)

[Claims] A magnetic recording and reproducing apparatus that records digital data to which a synchronization pattern and address control information are added on a magnetic tape so that the control information is at a predetermined position on a track, and reproduces the magnetic tape with a rotary head, block address prediction means for predicting the address recorded at the playback position according to the rotational position of the rotary head;
composite address value generation means for creating a composite address value from the reproduction address value read from the magnetic tape by the rotary head and the output address value; and an address for comparing the composite address value with the predicted address value by the block address prediction means. A block address generation device comprising: a value comparison means; and a selection means for selecting the composite address value as a new output address value only when a comparison error by the address value comparison means is within a predetermined range.