JPH0214471A - memory controller - Google Patents

Abstract

PURPOSE:To write a reproduced digital data to a RAM by a correct block address value by generating the most significant bit of a block address while the range of the block address is being limited by an address predicted by the rotating position of a rotary head. CONSTITUTION:The memory controller consists of a block address latch circuit 4, a block address counter circuit 6, a write signal generating circuit 10, a synthesized block address generating circuit 21 and address value comparator circuits 23, 24 or the like. Then the rotating position of a reproduction rotary head is detected and the recorded address is predicted by the detected position and the synthesized address is generated from the reproduced address and the output address. Then the synthesized address and the predicted address are compared and when the comparison error is within a prescribed range, the synthesized address is adopted as a new output address. Moreover, the output address and predicted address are compared and only when the comparison error is within a prescribed range, the write signal of a reproduced digital data is generated. Thus, the digital data is written only near the correct address.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory control device for recording and reproducing serial digital data.

BACKGROUND OF THE INVENTION Serial digital data recording and reproduction has been widely used in many fields, with one recent example being the digital audio tape recorder (DAT).

As an example, if we consider a rotary head type digital audio recorder (R-DAT), its recorded signals are serial digital data Do, as shown in FIG.
・・・・・・A synchronization signal 5YNC of a specific pattern is inserted into Dn at a block period Bt that is equally spaced in time, and in addition, a code ID (Identification) for identifying the contents recorded in the serial digital data is inserted.
, blow) address code BA (Blo)
ck Address), and an error detection code EDC (Error Detection Code) for ID and BA.
on Code). Each code is composed of 8 bits and is called a symbol.

FIG. 4 shows a block diagram of a conventional memory control device.

In FIG. 4, serial digital data during reproduction is inputted from an input terminal 2, a synchronizing signal is detected in a synchronizing signal detection circuit 3, and a signal phase-synchronized with the synchronizing signal is created.

The serial type digital data is latched by a block address latch circuit 4 into eight serial address codes by a latch pulse from a synchronization signal detection circuit 3. Further, the serial digital data is processed in a parity check circuit 5 by a pulse from the synchronization signal detection circuit 3, for example.
In the code configuration shown in FIG. 2, it is determined whether the even or odd parity is correct as expressed by P==W, ■W2 or P=W1 ■W2 (■ indicates exclusive OR). The output of the synchronization signal detection circuit 3 is input to the clock terminal of the block address color/return circuit 6, and is also input to the rotating head (not shown) via the input terminal 1.
A head switch pulse signal indicating the rotational position of the block address counter circuit 6 is input to the reset terminal of the block address counter circuit 6, and the contents of the counter of the block address counter circuit 60 are reset at the edge of the head switch pulse signal, and from then on, the counter is counted up using the synchronization signal as a clock. is reset at the edge of the RAD switch pulse signal to the next,
This has been repeated ever since. The output (8 bits) of the block address counter circuit 6 and the output (8 bits) of the block address latch circuit 4 are input to the block address mismatch circuit 8, which determines whether the block address values are the same. The output and the output of the parity check circuit 5 are input to the AND circuit 7, and if the parity check result is correct and the block address values do not match, the AND circuit 7 also generates a pulse, which is input to the load terminal of the block address counter circuit 6. The output (8 bits) of the block address latch circuit 4 is input to the data input terminal of the block address counter circuit 6.
The address value of the block address latch circuit 4 is loaded into the block address counter circuit 6. The output (8 bits) of the block address counter circuit 6 is outputted via the output terminal 9, and the RAM (
RlLndomAccesSMemory) Forms part of the address value when writing to.

Furthermore, the output of the synchronization signal detection circuit 3 and the output of the block address counter circuit 6 are input to the write signal generation circuit 10, and the output of the write signal generation circuit 10 is input to the output terminal 11.
The reproduced digital data is outputted via the RAM
It is used as a write signal when writing to.

By the way, in a magnetic recording and reproducing device that records and reproduces video signals on a magnetic tape using a rotating head, when recording and reproducing audio signals as digital signals, the analog audio signal is converted to a sampling frequency fs (eg, fs = 4a K).
In order to convert the video signal into a digital signal using Iz), the field frequency of the video signal fma (NTSC system fv = s e ,
94 Hz) is 800.8, so the number of data in the field is set to two types, large and small (for example, near 92 Hz).
and 810), dummy data is added to and recorded in fields with less audio data (fields with 792 data) to compensate for the insufficiency.

Since the information indicating whether the dummy data is added or not is recorded using the MSB of the 8 address codes shown in FIG. 2, the block address value is 7 bits. When the number is 135, it is recorded on the magnetic tape as (0-127.0-6).

Problems to be Solved by the Invention However, when digitally recording an audio signal in synchronization with a video signal as described above, the block address recorded on the magnetic tape has only 7 pits.
The problem is that the block address value (8 bits) during reproduction cannot be directly created from the recording block address value (7 bits).

The present invention has been made in view of the above-mentioned problems, and includes a block address generation circuit that generates a block address value when digitizing and recording/reproducing an audio signal simultaneously with a video signal, and a block address generation circuit that writes the reproduced digital data to a RAM. The present invention provides a memory control circuit having a write signal generation circuit that generates a write signal at a time.

Means for Solving the Problems In order to achieve the above object, the present invention provides a block address prediction means for predicting an address recorded at a playback position according to the rotational position of a rotary head, and a block address prediction means for predicting an address recorded at a reproduction position according to a rotational position of a rotary head, a composite address generation means for creating a composite address value from a reproduction address value and an output address value; a first address value comparison means for comparing the composite address value with a predicted address value by the block address prediction means; address selection means for setting the composite address value as a new output address value only when a comparison error by the value comparison means is within a predetermined range; and a second address selection means for comparing the output address value of the address selection means and the predicted address. address value comparison means; and write signal generation means for generating a write signal for writing reproduced digital data from the magnetic tape into the memory circuit only when the comparison error by the second address value comparison means is within a predetermined range. The structure is as follows.

Operation The present invention has the above-mentioned configuration when reproducing a magnetic tape on which a digital signal to which a synchronization pattern and an address are added is recorded by a rotary head so that the synchronization pattern and address are at a predetermined position on the track. , detects the rotational position of the rotary head that performs playback, predicts the address (8 bits) recorded based on the detected rotational position, and calculates the playback address value (7 bits) and output address value (8 bits). create a composite address value (8 bits) from the upper 1 bit of the
When the comparison error is within a predetermined range, the synthesized address value is adopted as the new output address value, so a correct address value is created.The output address value is further compared with the predicted address value, and only when the comparison error is within the predetermined range. Since a write signal for writing reproduced digital data into the RAM is generated, digital data can be written only in the vicinity of the correct address.

EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the memory control device of the present invention, and FIG. 2 is a waveform diagram of each part in FIG. 1.

In FIG. 1, serial digital data during reproduction is input from an input terminal 2, a synchronizing signal is detected in a synchronizing signal detection circuit 3, and a signal that is phase-synchronized with the synchronizing signal is created. The serial type digital data is sent to the synchronization signal detection circuit 3 in the block address latch circuit 4.
Eight address codes are latched by the latch pulse from.

Furthermore, the serial type digital data is processed by a pulse from the synchronization signal detection circuit 3 in a parity check circuit 6.
For example, in the code structure shown in FIG. 3, it is determined whether the parity is correct to even or odd parity as expressed by P=W, ■W2 or P=W, ■W2 (■ indicates exclusive OR). The output of the synchronization signal detection circuit 3 is input to the clock terminal of the block address counter circuit 6, and is also input to the rotating head (not shown) via the input terminal 1.
A head switch pulse signal (signal S1 shown in FIG. 2) indicating the rotational position of is input to the reset terminal of the block address counter circuit 6, and the contents of the counter of the block address counter circuit e are shown in analog form as shown in FIG. As shown in signal S2, it is reset by the head switch pulse signal, after which it is counted up using the synchronization signal as a clock signal, stops at the maximum value (134) of the block address, and is reset by the next head switch pulse signal.
This is repeated below. The output of the block address counter circuit 6 (lower 7 bits) and the output of the block address latch circuit 4 (lower 7 bits) are input to a block address mismatch circuit 8, which determines whether the block address values are the same. The output of the block address latch circuit 4 (lower 7 bits) and the output of the block address counter circuit 6 (higher 1 bit) are input to the composite block address generation circuit 21, and the most significant pit of the block address is input to the block address counter circuit 6. At the output, a composite block address value whose lower 7 bits are composed of the output of the block address latch circuit 4 is created. The reference block address generation circuit 22 is composed of a counter circuit, and input terminal 1
The head switch pulse signal from the counter is input to the reset terminal, counted up by the internal reference clock, and if the contents of the counter are shown in analog form as signal S3 in FIG. 2, it is reset by the head switch pulse signal.
Thereafter, the internal reference clock counts up and stops at the maximum value of the block address (13, 4), and by repeating this process, a block address value corresponding to the multi-rotation head position is generated. The output (8 bits) of the reference block address generation circuit 22 and the output (8 bits) of the composite block address generation circuit 21 are input to the first address value comparison circuit 23. Here, if the predicted 7th address value Nm of the reference block address generation circuit 22 and the composite address value NB of the composite block address generation circuit 21 are the
The address value comparison circuit 23 performs the following calculation N1=lNmu-NB1 to find the absolute value of the difference, and determines the magnitude of the calculation result 1 as a predetermined value N, *xy. The output of the parity check circuit 6, the output of the block address mismatch circuit 8, and the output of the first address value comparison circuit 23 are input to the AND circuit 7, and if the parity check result is correct, the block address values do not match, and N11xy > l NA -Nil l (the part inside the solid line centered on the dotted line of the signal S4 in FIG. 2) is established, a pulse is generated from the AND circuit 7 and input to the load terminal of the block address counter circuit 6. The output (8 bits) of the composite block address generation circuit 21 is input to the data input terminal of the block address counter circuit 6, and is loaded into the diblock address counter circuit 6 by the load pulse from the AND circuit 7. The output (8 bits) of the block address counter circuit 6 is outputted via the output terminal 9, and forms part of the address value when writing reproduced digital data to the RAM.

Furthermore, the output of the synchronization signal detection circuit 3 and the output of the block address counter circuit 6 are input to the write signal generation circuit 1o, and the output (8 bits) of the block address counter circuit 6 and the output (8 bits) of the reference block address generation circuit 22 are input to the write signal generation circuit 1o. bit) is input to the second address value comparison circuit 24. Here, the predicted address value N of the reference block address generation circuit 22 and the block address counter circuit 6
Assuming that the output address value Nc is, the second address value comparison circuit 24 performs the calculation Nz=lHAHa1 to find the absolute value of the difference shown below, and determines the size of the calculation result N2 from a predetermined value)T211XF. . The output of the write signal generation circuit 10 and the second
If the output of the address value comparison circuit 24 of A write signal is generated and output through the output terminal 11, and the readout digital data is stored in the RAM.
Used as a write signal when writing to.

Effects of the Invention As described above, according to the present invention, the uppermost pit of the block address value is created while limiting the range of the block address value using the address value predicted from the rotational position of the rotary head. Reproduced digital data can be written to RAM. In addition, even if the parity check is incorrectly determined to be correct and the block address value is corrected, the write signal will be generated only in a limited area of the output block address value with the predicted address value. RA playback digital data
Since the range written to M is limited to the vicinity of the predicted address value, error correction processing of the reproduced digital data written to the RAM is started even if one track of reproduced digital data is not completely written to the RAM. Therefore, the time from when the reproduced digital data is written to the RAM until the start of error correction can be greatly shortened. Therefore, the data processing time during playback associated with digital recording and playback of audio signals can be greatly reduced, so when recording and playing back video and audio signals, the processing delay time difference (' rD) can be made small, and in particular, even if the number of dubbings (n: number of times) increases, the processing delay time difference (Tnn = TnXn) between the audio signal and the video signal is also small, so the processing delay time difference is not noticeable to the viewer. This makes it possible to realize a playback device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory control device in an embodiment of the present invention, FIG. 2 is a waveform diagram of the main parts in FIG. 1,
FIG. 3 is a signal configuration diagram of serial digital data applied to the input terminal in FIG. 1, and FIG. 4 is a block diagram of a conventional memory control device. 1.2... Input terminal, 3... Synchronous signal detection circuit, 4... Flock address latch circuit, 5... Parity check circuit, 6... ...Block address counter circuit, 7, 25...A
ND circuit, 8...Block address mismatch circuit, 9, 11...Output terminal, 1°...Write signal generation circuit, 21.Mountain...Synthetic block address generation circuit , 22... reference block address generation circuit, 23... first address value comparison circuit, 24
...Second address value comparison circuit.

Claims (1)

[Claims] A magnetic recording and reproducing apparatus that records digital data to which control information such as a synchronization pattern and an address is added onto a magnetic tape so that the control information is located at a predetermined position on a track, and that reproduces the magnetic tape with a rotary head. block address prediction means for predicting the address recorded at a position according to the rotational position of the rotary head; and creating a composite address value from a playback address value and an output address value read from the magnetic tape by the rotary head. a composite address value generating means; a first address value comparing means for comparing the composite address value with the predicted address value by the block address predicting means; address selection means for setting the composite address value as a new output address value only when the combined address value is a new output address value; second address value comparison means for comparing the output address value of the address selection means and the predicted address value; A memory control device comprising write signal generating means for generating a write signal for writing reproduced digital data from the magnetic tape into a memory circuit only when a comparison error by the value comparing means is within a predetermined range.