JPH0122941B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is an intermediary between an input/output device and a main memory, and transfers data between the input/output device in bytes and between the main memory and the main memory in units of words. The present invention relates to a data transfer control device (data channel device) that performs.

A data channel device is interposed between an input/output device and a main storage device, and functions to control data transfer between these devices. Regulations are necessary. In other words, if the data handled by the input/output device is in bytes, but the data in the main memory is in words, the direction in which the byte-based data is stored in the main memory and the word data from the main memory are different. This means that the byte-by-byte sending order direction to the input/output device must be appropriately predetermined. Normally, word data read from main memory is sequentially sent from the upper byte position to the lower byte position, and the byte data is sequentially sent to the input/output device.However, when storing word data, the input/output device similarly starts from the upper byte position. Byte data is sequentially sent toward the lower byte position to form word data and to be stored. Of course, on the contrary, it is also possible to read and store byte data from the lower byte position to the upper byte position.

FIG. 1 shows the system configuration of a data processing system including a data channel device (DCH). According to this, the data channel device 3 starts the control operation in response to a start input/output command from the central controller (CC) 2, and then automatically starts the command address word ( CAW). The contents of the command address word are the storage memory address of the channel control word (CCW) on the main memory device 1, and the channel control word is read out indirectly based on this memory address. FIG. 2 shows the storage memory address relationship between the command address word and the channel control word (in this example, two words) on the main memory device 1. As shown in FIG. 3a, since the content stored at memory address A is the first memory address B of the channel control word, memory addresses B, B+1
Channel control words CCW0 and CCW1 are read out. Figures 3b and 3c show the data formats of these channel control words CCW0 and CCW1, including a command identification (CMC) part that specifies reading, writing, etc., and a flag (FLG) part that specifies a variation of DCH operation. ) part, data transfer amount (WC) part, data transfer start address (DA) part on the main memory, and data transfer start byte position designation (SBC) part on the main memory. The data channel device controls data transfer between the input/output device (IO) 4 and the main storage device 1 based on this control information.

Figure 4 shows the byte positions and the allocation to each byte position when one word consists of 4 bytes.
Indicates the relationship with SBC. 31-24 as shown
The bit positions (most significant byte positions), 23 to 16 bit positions, 15 to 8 bit positions, and 7 to 0 bit positions (lowest byte positions) are 0, 3, 2, and 1, respectively.
This is the one to which an SBC has been assigned. When SBC is specified, the order direction when reading and storing data in units of bytes on the main memory device 1 is as follows, for example.

That is, FIG. 5a shows the order direction at the time of reading and storing when the value of SBC is 0. In this example, data is read out and stored in byte units in advance from the upper byte position to the lower byte position. Therefore, when the CMC is in write mode, the data channel device first reads one word of data at memory address DA and stores it in the buffer, then extracts the byte data from the most significant byte position of the buffer register and sends it to the input/output device. After that, byte data is transferred sequentially toward the lower byte position. Once the transfer of one word of data at memory address DA is completed, similar reading from the main memory and transfer to the input/output device are performed every time the memory address is sequentially updated by the amount specified by WC. That's why. Also,
When the CMC is in read mode, the byte data from the input/output device is first stored in the most significant byte position of the buffer register in the data channel device, and then stored sequentially toward the lower byte position to form one word. Store it in the storage device. When data storage at a memory address is completed, similar storage control is performed while sequentially updating the memory address by the amount specified by the WC. FIG. 5b shows the order of reading and storing when the value of SBC is 3, but this is clearer than the case shown in FIG. 5a, so no special explanation is required. In addition, in FIGS. 5a and 5b, the numbers in circles indicate the order of reading and storing data in units of bytes.

As described above, conventionally, the order direction of reading and storing byte unit data on one word of the main memory device is fixed from the upper byte position to the lower byte position, or vice versa. However, if the order direction is fixed, there is a problem in terms of compatibility. This is because, assuming a data processing system in which the reading and storing order directions are mutually opposite, when a recording medium recorded by the input/output device of one data processing system is read by the other data processing system, the data This is because the order direction of the data will be completely reversed and it will be of no use as data. If the input/output device is a communication control device, it cannot be directly connected to other data processing systems.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer control device that allows the reading and storing order of byte unit data on one word of a storage device to be set in any direction.

For this purpose, the present invention newly provides a data editing order control flag in the channel control word, and the state of this flag controls the order direction of reading and storing byte unit data on one word of the storage device. This is how it was done.

The present invention will be explained below with reference to FIGS. 6 to 9.

First, FIGS. 6a and 6b show an example of the data format of channel control words CCW0 and CCW1 according to the present invention. What is substantially different from what is shown in Figures 3b and 3c is the channel control word CCW0.
A data editing order control flag (BPF) is newly provided as 1-bit data.
The order direction is controlled depending on whether this flag is in the set state or the reset state, but if we assume that the order direction when the flag is in the reset state is from the upper byte position to the lower byte position, then The order direction in the set state is defined as the direction from the lower byte position to the upper byte position. Figure 7 shows the relationship between the byte position and SBC when the order direction is from the lower byte position to the upper byte position.
It is clear from the above explanation that if the value of SBC is 0 or 2, the order of reading and storing will be as shown in FIGS. 8a and 8b, respectively. Further, when the order direction is from the upper byte position to the lower byte position, it is as explained in FIGS. 4 and 5 a and b. What should be noted here is that if the order direction is reversed, the allocation will be made to the byte position.
As is clear from Figures 4 and 7, the SBC value also changes. Therefore, this must also be taken into consideration when controlling the order direction.

FIG. 9 is an extracted diagram showing the essential parts of the data channel device according to the present invention as an example. Since only CCW0 is directly related to the present invention among the two-word channel control word, data transfer control is performed based on the control information contained therein. The most important thing in this control is how to generate the byte position selection signal.

Byte position selection signals BP0 to BP3 can be easily generated from 2-bit data of SBC and 1-bit data of BPF. That is, 2 of SBC included in CCW0
The bit data is preset to flip-flops 5 and 6, which constitute a quaternary down counter, respectively, and the outputs of the flip-flops 5 and 6 are input to AND gates (including 2-input negation and 1-input negation) 9 to 12.
It is now decoded by AND gates 9 to 12 are designed to output decoded outputs only when the outputs of flip-flops 5 and 6 are 0, 1, 2, and 3, respectively. Here, the output of the flip-flop 7 to which the 1-bit data of the BPF is set is used as the gate control signal for the AND gate (including 1-input negation) 1.
3 to 16 and 17 to 20 as shown in the figure, and the byte positions shown in Figures 4 and 7.
By inputting the outputs of AND gates 9 to 12 to AND gates 13 to 20 in a predetermined relationship in consideration of the relationship with SBC, the target byte position selection signals BP0 to BP3 can be input to the OR gates 21 and 20, respectively.
~24. In this case, the byte position selection signals BP0 to BP3 correspond to the 31st to 24th bit positions and the 7th to 0th bit positions on one word of the main memory, respectively.
It is used as a gate control signal to select the bit position, 15th to 8th bit position, and 23rd to 16th bit position.

By the way, in general, in a data channel device, data is transferred to and from the main memory via a 1-word buffer register 34, and data is transferred to and from an input/output device via a 1-byte buffer register. 35. Therefore, these buffer registers 3
The order direction of reading and storing byte unit data is controlled between 4 and 35.
When the CMC is in write mode, data read from the main memory in word units is temporarily stored in the buffer register 34 and then transferred in byte units to the input/output device via the buffer register 35. Transfer direction control in this case depends on the mode state of CMC. Since the flip-flop 8 is in the set state in the write mode,
Data can be transferred to the input/output device via AND gates 29 to 32 and OR gate 33. However, the order in which the 4-byte data in the buffer register 34 is transferred is determined by the byte position selection signals BP0 to BP.
It depends on 3. For example, when the value of SBC is 3 and the data state of BPF is "0", that is, the flip-flop 7 is in the reset state, the byte position selection signals are first output in the order of BP3, BP2, and BP1. gate 30
32 are sequentially opened, thereby transferring 3-byte data corresponding to memory address DA in a predetermined order. After this, 4-byte data corresponding to memory address DA+1 is transferred and stored in the buffer register 34, but for this, BP0, BP
By sequentially generating byte position selection signals in the order of 3, BP2, and BP1, 4-byte data can be transferred in a predetermined order. Thereafter, the same control as in the case of memory address DA+1 may be performed every time the memory address is updated until the final memory address is reached.

Also, when the value of SBC is 3 and flip-flop 7 is in the set state, first BP2, BP3, BP
0, therefore, the AND gates 31, 30, and 29 are sequentially opened, and the 3-byte data corresponding to the memory address DA is transferred in a predetermined order. After this, BP is used every time the memory address is updated until the final memory address specified by WC is reached.
Byte position selection signals 1, BP2, BP3, and BP0 are sequentially generated. By counting down the aforementioned down counter by 1 each time one byte of data is transferred, desired byte position selection signals are sequentially generated.

When the CMC is in the write mode, the above is the case, but when the CMC is in the read mode, the data in bytes from the input/output device is stored in the buffer register 3.
5, the data is once stored in the buffer register 34, and then stored in the main memory unit in word units. That is, in this case, since the flip-flop 8 is in the reset state, byte unit data from the input/output device is sent to the buffer register 35, the AND gates (1 input negation) 25 to 28, and the buffer register 3.
The data is stored in the main storage device via 4. In this case as well, the byte position selection signal determines in which byte position of the 4-byte capacity buffer register 34 the byte unit data transferred in time series from the input/output device is temporarily stored. It's on. For example SBC
Assuming that the value of is 3 and flip-flop 7 is in the set state, the memory address
Immediately before a write access is executed to DA, byte position selection signals BP2, BP3, and BP0 are generated in sequence, and therefore, AND gates 27, 26, and 25 are opened in sequence to read 3-byte data. The data are stored in the buffer register 34 in a predetermined order. Those 3 for memory address DA
After the byte data is stored, BP1, BP2,
It is sufficient to sequentially generate the byte position selection signals BP3 and BP0.

As explained above, the present invention provides a data editing order control flag in the channel control word, and depending on the state of this flag, the word data read from the main memory is processed in byte units toward the input/output device. The transfer order and the storage position order on word data of byte data transferred from the input/output device to the main storage device are controlled. According to the present invention, byte unit data is transferred to the input/output device in a completely reverse order using the data editing order control flag, and when forming word data, it may be stored in a completely reverse position order. Since it is possible to do so, it has the effect of eliminating the drawbacks that have been seen in the past.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the system configuration of a data processing system including a data channel device, and FIG.
A diagram showing the storage memory address relationship of the channel command word and channel control word that the data channel device reads from the main memory. Figure 3a, b, and c are data of the command address word (CAW) and channel control words CCW0 and CCW1, respectively. Figure 4, which shows the format, is a diagram showing the relationship between the data transfer start byte position designation control information (SBC) assigned to each byte position and that byte position when one word consists of 4 bytes. , Figure 5a,
Figures 6a and 6b are diagrams showing the reading order and storage order of byte unit data on the main memory when the SBC values are 0 and 3, respectively.
Channel control word CCW0, respectively according to the present invention.
Figure 7, which shows the data format of CCW1, is a diagram showing the relationship between the SBC allocated to each byte position and the byte position when the order of reading and storing byte unit data is reversed. , Figures 8a and 8b show the reading order of byte unit data on the main memory when the SBC values are 0 and 2, respectively, when the order of reading and storing byte unit data is reversed. FIG. 9, a diagram showing the storage order, is a diagram showing an example of the essential parts of the data channel device according to the present invention. 5~8...Flip Flop, 9~20, 25~
32...AND gate, 21-24, 33...OR gate, 34,35...Buffer register.

Claims (1)

[Claims] 1 Interposed between the input/output device and the main storage device, and according to the control content indicated in the channel control word read from the main storage device, data is transmitted between the input/output device and the main storage device in byte units. In a data transfer control device that transfers data in units of words, a data editing order control flag is provided in the channel control word, and the word data read from the main memory is controlled depending on whether the flag is set or not. The order of transfer in the direction of the input/output device in units of bytes,
1. A data transfer control device comprising means for controlling the storage position order of byte data on word data transferred from an input/output device to a main storage device.