JPH01231145A - Information processor - Google Patents

Abstract

PURPOSE:To prevent the competition of a memory and to prevent deterioration of the processing capacity by executing an access first to other module which is not showing a busy state, when a memory module to be brought to access is in a busy state. CONSTITUTION:A processor 1 reads out memory constituting information in a memory constitution control register 12 by a memory constitution read-out instruction 11, holds it in a memory constituting information store register 13, and also, responds to a request signal 15 and executes an access to a bank of a module in a memory device 2. In such a case, an access sequence changing means 16 in the processor 1 changes the sequence for executing the access by the memory constituting information in the register 13 and a busy state display of a busy state detecting means 14, and the access is executed first to the module which is not showing a busy state.

Description

DETAILED DESCRIPTION OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device, and more particularly to an information processing device having a memory device composed of a plurality of independently accessible modules.

Conventionally, this type of information processing equipment has not been provided with a function to check the configuration of modules within the memory device, and even when the configuration of the memory device changes due to degenerate operation, etc. Information such as access was processed using the same algorithm as before the change. Therefore, when a module in a busy state is accessed, memory contention occurs, and control is performed such that the sending of a request signal is made to wait until the module becomes free.

The conventional access operation is shown in Figs. 4, 5, and 6.
This will be explained using FIG. 7 and FIG. 4 and 5 are conceptual diagrams showing the configuration of modules in the memory device 2.
Assuming a 256 megabyte memory device in □ in FIG. 1, if it is divided into 8 modules and each module is composed of 16 banks, the total will be 128 banks. Then, bank addresses are assigned as shown in FIG. 4, with the first bank address of the first module (1) being r□, and the bank address "1" being taken from the next module.

When bank addresses 2 and subsequent are assigned in the same manner, the bank address of the last module becomes "7".

The next bank address "8" returns to the first module and is assigned to a bank different from bank address "0". Thereafter, 128 banks are addressed in the same manner.

Here, bank addresses 'IJ,'3J,'5J,'7
”, “8”, and “10”, if the memory device configuration is as shown in Figure 4, no memory contention will occur, so It becomes possible to send a request signal to all banks every cycle. However, if the configuration of the memory device is as shown in Figure 5 due to memory degeneration, etc., bank addresses "1" and "r5."
7" will cause memory contention.

That is, while bank address "1" is in a busy state, bank address "5" cannot be accessed, and while bank address "3" is in a busy state, bank address "7" cannot be accessed. Therefore, as shown in Figure 7, access to bank address "5" is started after access to bank address "1" is completed, and access to "7" is started after access to bank address "3" is completed. In order to start access, requests cannot be sent to the memory device every cycle, resulting in empty cycles.

Therefore, depending on the configuration of the memory device, memory contention frequently occurs, resulting in a reduction in processing performance.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing device that can prevent memory contention and reduce processing performance.

The information processing device of the present invention has a storage means made up of a plurality of independently accessible modules, and accesses the storage means in response to request information indicating a module to be accessed. an information processing device, comprising: a busy state detection means for detecting whether the module to be accessed is in a busy state; and a busy state is indicated when a detection result of the busy state detection means indicates a busy state. The present invention is characterized by comprising an execution order changing means for first accessing modules that are not currently accessed.

U top Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a system diagram showing the configuration of an embodiment of an information processing device according to the present invention. In FIG. 1, the information processing device according to an embodiment of the present invention includes a processing device 1 that processes information such as access, Memory device 2 composed of multiple modules
and a memory configuration control register 12 which holds memory configuration information indicating the configuration within the memory device T12 and whose contents are rewritten according to changes in the configuration within the memory device T12.

The processing device 1 has a memory configuration read instruction 11,
This memory configuration read command 11 reads the memory configuration information in the memory configuration control register 12 and holds it in the memory configuration information storage register 13.

Further, the processing device 1 accesses a bank of modules in the memory device 2 in response to a request signal 15. Additionally, the processing device 1 has a busy state detection means 14.

The busy state detection means 14 detects whether the module to be accessed is busy in response to the request signal 15. The access order change 'means 16 is
Memory contention is prevented by changing the access order according to the memory configuration information in the memory configuration information storage register 13 and the detection result of the busy state detection means 14.

Next, the memory configuration control register 12 and the internal configuration of the memory device 2 will be explained using FIGS. 2, 3, 4, and 5. 2 and 3 are conceptual diagrams showing memory configuration information in the memory configuration control register 12. FIG. Also,
4 and 5 are conceptual diagrams showing the configuration of modules within the memory device 2. FIG.

In FIGS. 2 and 3, "1" indicates that the corresponding module is valid, and r□ indicates invalid. Therefore, the configuration of the modules in the memory device 2 is as shown in FIG. 4. If so, the memory configuration information will be as shown in FIG. Furthermore, if the configuration of the modules in the memory device 2 is as shown in FIG. 5, the memory configuration information will be as shown in FIG. 3.

In the present invention, the order in which the request signals are sent is changed by the access order changing means 16 in accordance with this memory configuration information and the detection result of the busy state detecting means 14.

The access order changing means 16 is provided with a compiler of an algorithm that does not cause memory contention, corresponding to each memory configuration, and the memory configuration control register 12
Empty cycles of request signals are eliminated by switching the algorithm according to the message configuration information read from the memory.

Next, switching of the algorithm of the access order changing means 16 will be explained using FIG. 9, FIG. 10, and FIG. 11. FIG. 9 is a flowchart showing the processing operation of the information processing apparatus according to this embodiment.

Further, FIG. 10 is a flowchart showing the processing operation of step 902 in FIG. 9, and FIG. 11 is a flowchart showing the processing operation of step 907 in FIG.

In FIG. 9, the memory configuration information read from the memory configuration control register 12 is stored in the memory configuration information storage register 13.
After being stored in the memory device g12, its contents are determined by the access order changing means 16 (step 901).As a result, when the memory configuration information is as shown in FIG. When the module configuration is as shown in FIG. 4, execute algorithm modification A (step 9G2), and when the memory configuration information is as shown in FIG. 3, the memory configuration r! When the configuration of the modules in 12 is as shown in FIG. 5, algorithm modification B is executed (step 907).

In algorithm modification A, as shown in FIG. 10, it is first checked in response to a request (step 101) which module the bank address to be accessed belongs to (step 102).

In this case, there are 8 modules, so if the bank address number is B and the module number is M, then M = (B) no
It becomes 6.8.

Next, check whether the bank address is in the same module as the bank address accessed by the previous request (step 103).
, if they are in the same module, there will be a memory conflict (busy state), so the request will be postponed (step 103 → 101); on the other hand, if they are not in the same module, the request will be sent (step 103).
→104).

This operation is repeated to change the order in which requests are sent and reduce memory contention.

Furthermore, in algorithm modification B, as shown in FIG. 11, it is first checked in response to a request (step 111) which module the bank address to be accessed belongs to (step 112).

In this case, there are 4 modules, so if the bank address number is B and the module number is M, then M = (BlOd
It becomes 4.

Next, check whether the bank is in the same module as the bank address accessed by the previous request (step 113). If it is in the same module, there will be a memory conflict (busy state), so Postpone the request (Step 1)
13 → 11i), on the other hand, if the module is not in the same module, the request is sent (step 113 → 114
).

In other words, memory contention is reduced by selecting an algorithm for checking depending on the content of memory configuration information.

In FIG. 9, algorithm modification A (step 902
) or when algorithm modification B (step 907) is completed, memory access is started (step 903).
or 908), if the bank address is busy, the access is postponed to step 904.
→903 or 909→908), and if it is not busy, access the bank address (step 90
5 or 910), predetermined processing is performed (step 906 or 911).

By performing the above processing, when the memory configuration information is as shown in FIG. 3, that is, when the module configuration in the memory device 2 is as shown in FIG. .

[3J, "5J, '7J +"8J and "10
When there is a program that accesses ", the access order changing means 16 changes the access order and accesses as shown in FIG. 8, thereby preventing memory contention and eliminating empty request cycles. I can do it,
This makes it possible to prevent a decline in processing capacity.

1 As explained above, the present invention prevents memory contention and reduces processing performance by changing the access order according to memory configuration information indicating the configuration of modules in a memory device. The effect is that it can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing the configuration of an information processing device according to an embodiment of the present invention, FIGS. 2 and 3 are conceptual diagrams showing memory configuration information in a memory device, and FIGS. 4 and 5 are diagrams showing the memory device. 6, 7 and 8 are time charts showing the processing time of the information processing apparatus according to the embodiment of the present invention, and FIGS. 9, 10 and 11 1 is a flowchart showing processing operations of an information processing apparatus according to an embodiment of the present invention. Explanation of symbols of main parts 1...Processing device 2...Memory device 12...Memory configuration control register 14...
... Busy state detection means 16 ... Access order change means Applicant: NEC Corporation (1 other person)

Claims (1)

[Claims] An information processing apparatus having a storage means configured from a plurality of independently accessible modules, and accessing the storage means in response to request information indicating a module to be accessed, the module to be accessed. a busy state detection means for detecting whether or not the busy state detection means is in a busy state; and execution that first accesses a module that does not indicate a busy state when the detection result of the busy state detection means indicates a busy state. An information processing device comprising: order changing means.