JPH02193235A - Detection of bus access exception - Google Patents

Abstract

PURPOSE:To improve the instruction execution efficiency, to simplify the hardware constitution, and to reduce the burden on a CPU by detecting a bus access exception only at the time of transfer of data including a word as the access object even in the case of the occurrence of bus error. CONSTITUTION:Only at the time of transfer of the word including the access object from a main storage device 15 to a cache 27, a bus access exception is detected when bus error occurs; but a bus access exception is not detected though bus error occurs at the time of transfer of a word, which does not include the access object, from the main storage device 15 to the cache 27. Consequently, only a minimum required exception processing is performed with respect to execution of a program in a central processing unit 11, and unnecessary exception processing is not started. Thus, the instruction execution efficiency of the central processing unit 11 is improved, and the hardware constitution is simplified, and the burden on the central processing unit 11 is reduced.

Description

[Detailed Description of the Invention] [Summary] A bus access exception detection method for a computer system having a cache that buffers data in main memory and supplies it to a central processing unit improves the efficiency of instruction execution and improves the hardware configuration. In order to simplify the process and reduce the burden on the central processing unit, when an access target to be accessed by the central processing unit does not exist in the cache, a multi-word block containing the access target is transferred word by word from the main memory to the cache. , only the access target is transferred to the central processing unit, and when a bus error occurs during transfer from the main memory to the cache, a bus access exception is detected and the central processing unit handles the exception. In a bus access exception detection method for a computer system, a bus access exception is detected if the bus error occurs only when a word containing the access target is transferred from the main memory to the cache, and a bus access exception is detected when the word that does not include the access target is transferred from the main memory to the cache. 4. The configuration is such that a bus access exception is not detected even if the bus error occurs during transfer to Yash.

[Industrial application field]

The present invention relates to a bus access exception detection method, and more particularly to a bus access exception detection method for a computer system having a cache that buffers data in main memory and supplies it to a central processing unit.

There is a computer system that has a central processing unit (CPU), a main memory, and a cache that buffers data in the main memory. In such systems, the cache uses CPU
When data to be used is not stored, data is transferred from main memory to cache in blocks.

(Prior art) In the case of a system that uses a cache, the size of normal access data is, for example, a maximum of 4 bytes, whereas the unit of data transfer from main memory to the cache, or block, is, for example, 16 bytes, which is smaller than the access data size. big. If the bus between the main memory and the cache is, for example, 4 bytes, which is smaller than the above block, data transfer of 4 bytes is repeated four times using the bus. Normally, in this transfer, the accessed data is transferred first, and then the remaining data of the block is transferred.

Conventionally, if a bus error occurs during any of the four data transfers described above, the CPU performs exception processing.

[Problem to be solved by the invention]

However, even if a bus error occurs during the transfer of the remaining data that is transferred after the accessed data, as long as this remaining data is not registered in the cache, CPLJ will continue processing without any problem. Instead, there is a problem in that the execution of instructions by the CPU is unnecessarily interrupted due to exception handling, which deteriorates the efficiency of instruction execution.

Also, 4. from the main memory. Data transfer to Yash is done by CPU
The cache system performs this in accordance with the instructions given by the cache system, and the CPU performs other processing after obtaining the accessed data. Therefore, even if a bus error occurs during the transfer of the remaining data, the program counter will indicate the bus error. It does not refer to the instruction to the cache system that causes the error, and the hardware configuration is complicated because the cause of the error cannot be known unless the program counter value is stored separately until all data transfer to the cache is completed. CPL
There was a problem that the burden on I would increase.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a bus access exception detection method that improves the efficiency of instruction execution, simplifies the hardware configuration, and reduces the burden on the CPU.

[Means to solve the problem]

The bus access exception detection method of the present invention includes a central processing unit (
The access target of 11) is the cache (27
), transfers a multi-word block containing the access target from the main memory (15) word by word to the cache (27), transfers only the access target among them to the central processing unit (11), and Main memory (15
) to the cache (27), a bus access exception is detected and the central processing unit (
In the bus access exception detection method for a computer system that performs exception handling in 11), if the bus error occurs only when the word containing the access target is transferred from the main storage device (15) to the cache (27), a bus access exception is detected. is detected, and the main memory of the word that does not contain the access target (
Even if the bus error occurs during transfer from file 15) to file 1 (27), no bus access exception is detected.

(Function) In the method of the present invention, even if a bus error occurs, bus access exception detection is performed only during data transfer of the word containing the access target. Only the processing is performed, unnecessary exception handling is not started, improving the efficiency of instruction execution, and there is no need to store the value of the program counter until the transfer of one block to the cache (27) is completed, resulting in a hardware configuration. The load on the instruction and execution unit 11 is reduced.

〔Example〕

FIG. 2 shows a configuration diagram of a computer system to which the method of the present invention is applied.

In the figure, a microprocessor 10 is composed of an instruction and execution unit (IU/ELI) 11 as a CPLJ, a storage unit (SU) 12 as a cache system, and a bus unit (BU) 13. The bus unit 13 is connected to a bus 14 outside the CPL 110, and the bus 14 includes a main storage device 15 and peripheral bags such as input/output circuits @1.
6 is connected.

FIG. 3 shows a block diagram of the storage unit.

In the figure, addresses, sizes, read requests, write requests, and write data are input from the instruction and execution unit 11 to terminals 20.21, 22.23.24, respectively. The address is latched in the latch circuit 25 and cross-checked to the cross-check circuit 2.
6. The signal is supplied to the carriage 127 and also to the bus unit 13 from the terminal 28. The size (number of bytes) is latched by the latch circuit 29 and supplied to the cross check circuit 26. Read request and write request are each made by latch circuit 3.
1.32 and supplied to the bus access control circuit 33. In addition, the write data is supplied to the selector 34 and latched by the write data latch circuit 35 to the terminal 3.
6 to the bus unit 13.

The cross check circuit 26 checks the presence or absence of word crosses and block crosses from the address and size. Word crossing is when the data to be accessed straddles word (-4 byte) boundaries, and blocks (=16 bytes) are accessed.
This is the case when the data straddles a byte) boundary. The cross check circuit 26 notifies the instruction and execution unit from a terminal 40 when there is a block cross, and notifies the data transfer circuit 41 when there is a word cross, and stores the block size, which is the number of bytes to be accessed in the block, in the cache 27. and informs the data transfer control circuit 41.

The data transfer control circuit 41 transfers the block size to a terminal 42.
to the bus unit 13, and also to the bus unit 13.
Every time one word of data transfer is completed, a completion notification is supplied via the terminal 43, and it is determined whether the instruction and access request from the execution unit 11 has been completed, and if it is not completed, the bus 1 error detection circuit 45 When the instruction is completed, the instruction and execution unit 11 is notified of the completion of data transfer from the terminal 46. Also, when transferring each word, cache 2
7 and read data latch circuit 47 respectively.

Bus access control circuit 33 includes instruction and execution unit 11
If there is no data in the cache 27, an access command is issued to the bus unit 13 from the terminal 48, and the bus error detection circuit 45 is informed whether reading or writing is in progress. The command completion notification is instructed to register the transferred data in the cache 27. When the bus error detection circuit 45 receives a bus error signal from the bus unit 13 via the terminal 51, it notifies the instruction and execution unit 11 of the bus error from the terminal 52 when the data transfer is not completed, and instructs the activation of exception processing.

Read data coming from the bus unit 13 via the terminal 55 is transferred to the read data latch circuit 47 and the selector 34.
The data selected by the selector 34 is written into the cache 27. The cache 27 has a capacity of, for example, 2 bytes, and is divided into blocks with 4 bytes as 1 word and 4 words as 1 block. There is. Note that the data transfer unit is 4 bytes.

The data read from the cache 27 and the data from the single data latch circuit 47 are supplied to the selector 56, and the data selected here is supplied from the terminal 57 to the instruction and execution unit 57.

FIGS. 1A to 1C show flowcharts of read processing of the storage unit 12 to which the method of the present invention is applied.

In FIG. 1(A), the storage unit 12 first receives a read request, address Δ, and size S from the instruction and execution unit (ILJ/EtJ) 11 (step 60), and from the address A and size S, word cross and block cross. The presence or absence of the information is checked (step 61). In step 62, it is determined whether or not there is a block cross, and only when there is a block cross, this is notified to the instruction and execution unit 11 (step 63), and the size S is changed to the size within the block (step 64).

Thereafter, the cache 27 is searched using the address A (step 65), and it is determined whether there is data to be accessed (hit) in the cache (step 66). If it is a hit, the data read from the cache 27 is supplied to the instruction and execution unit 11, and the end of the data transfer is notified (step 67), and the process ends. If not, an access command for address A1 size S1 read access is sent to the bus unit (step 6B).

Next, in step 69 of FIG. 1(B), the end of word transfer of the first word from the bus unit 13 is received, the read data is latched in the read data latch circuit 47 and the cache 27, and then the read data is latched in the read data latch circuit 47 and the cache 27. The presence or absence of a bus error signal is determined (step 71). If there is a bus error in the transfer of the first word, a bus error notification is sent to the instruction and execution unit 11 (step 72), and the process is terminated (1). If there is no bus error, it is determined whether there is a word cross (step 73).

If there is a word cross, the end of word transfer of the second word is received from the bus unit 13, and the read data from the bus unit 13 and the link in the read data wrap circuit 47 are transferred.
merges the data requested for access from the read data and transfers it to the instruction and execution unit 11, latches the read data from the bus unit 13 in the cache 27, and notifies the instruction and execution unit 11 that the data transfer is completed ( Step 74). After this, Pasco determines whether there is a bus error signal from the unit 13 (step 75),
If there is a bus error, the instruction and execution unit 11 is notified of the bus error (step 76), and the process ends.

If it is determined in step 73 that there is no word cross, the read data of the read data latch circuit 47 is transferred to the instruction and execution unit 11, and the instruction and execution]-nit 11
The end of data transfer is notified to (step 77). Step 7
8), the presence or absence of a bus error signal from the bus unit 13 is determined; step 79); even if there is a bus error, the process is terminated without notifying the instruction and execution unit 11;

If it is determined in step 75 or 79 that there is no bus error, the process advances to step 81 in FIG. . Thereafter, if it is determined in step 83 that there is a bus error signal, the process is terminated without notifying the instruction and execution unit 11 of the bus error.

Here, if it is determined that there is no bus error, the process proceeds to step 83, where the end of word transfer of the fourth word is received and the read data from the bus unit 13 is latched into the cache 27. Thereafter, if it is determined in step 84 that there is a bus error signal, the process is terminated without notifying the instruction and execution unit 11 of the bus error. If there is no bus error, the 4-word data latched in the cache 27 by the upload 85 is tagged as data at address A and registered in the cache 27, and the process ends.

Here, one block of bytes (0) shown in FIG. 4(A)
~ (F) is byte (0) ~ (3), <4) ~ (7), (
8) ~ (B), (C) ~ (F) 4 bytes each constitute a word, and when satin bytes (5) and (6) are access data, there is no word cross (, 1st Word bytes (4) to (7), second word bytes (8) to (
B), the third word is bytes (C) to (F), and the fourth word is bytes (0) to (3), and data is transferred to the storage unit 12 in the order of . At this time, the second
~ Even if there is a bus error in the third word, the instruction and execution unit 11 is not notified of the bus error.

As shown in the same figure (B), the access data is byte (7)
~(A) If there is a word cross, the first word is byte (4)~(7), the second word is byte (8)~(
Data transfer is performed as B), bytes (7) to (A) are merged in the read data latch circuit 47 and supplied to the instruction and execution unit 11, and then the third word (bytes (C) to (F)) , 49th code (byte (0) ~ (
3)) Data transfer is performed. At this time, the third. Even if there is a bus error in the fourth word, the instruction and execution unit 11 is not notified of the bus error.

In addition, as shown in the same figure (C), if the access data has a block cross in bytes (E) and (F) of the first block and bytes (10) and (11) of the second block, the access data of the first block is Bytes (C) to (F) are the first word.■
The data transfer of the 19th - dollar 4th word is performed in the order of ~■, and the instruction and execution unit 11 that received the notification of the block cross makes an access request again, and as a result, the bytes (10) ~ ( 13) is the first word, and data transfer of the 19th to 4th words is performed in the order of ■ to ■. At this time, the second to fourth blocks of the first block
Even if there is a bus error in the word and the second to fourth words of the second block, the instruction and execution unit 11 is not notified of the bus error.

In this way, even if there is a bus error signal in data transfer other than the data that is directly accessed, the instruction and execution unit 11 is not notified of the bus error, so the instruction and execution unit 11 does not receive a bus error notification from the perspective of program execution. Only the minimum necessary exception handling is performed, unnecessary exception handling is not activated, and the efficiency of instruction execution is improved. Furthermore, after the data to be accessed is transferred to the instruction and execution unit 11, the instruction and execution unit 11 increments the program counter, so the value of the program counter is stored until all data transfer of one block to the cache is completed. This simplifies the hardware configuration and reduces the burden on the CPU.

(Effects of the Invention) As described above, according to the bus access exception detection method of the present invention, the efficiency of instruction execution of the central processing unit is improved, the hardware configuration is simplified, and the burden on the central processing unit can be reduced. It is extremely useful in practice.

[Brief explanation of the drawing]

1 is a 70-chart of read processing of a storage unit to which the method of the present invention is applied; FIG. 2 is a configuration diagram of a computer system to which the method of the present invention is applied; FIG. 3 is a block diagram of the storage unit in FIG. FIG. 4 is a diagram for explaining the method of the present invention. In the figure, 10 is a microprocessor, 11 is an instruction and execution unit (central processing unit), 12 is a storage unit, 13 is a bus unit, 14 is a bus, 15 is a main storage device, 27 is a cache, and 60 to 85 are steps. I'm in charge.

Claims (1)

[Claims] When the access target to be accessed by the central processing unit (11) does not exist in the cache (27), the main storage device (15)
A block having a plurality of words including the access target is transferred word by word to the cache (27), and only the access target among them is transferred to the central processing unit (11),
and a bus access exception detection method for a computer system, which detects a bus access exception when a bus error occurs during transfer from the main storage device (15) to the cache (27), and performs exception handling in the central processing unit (11). In this case, if the bus error occurs only when the word including the access target is transferred from the main storage device (15) to the cache (27), a bus access exception is detected, and the target of the word that does not include the access target is detected. Main memory (15
) to the cache (27), even if the bus error occurs, the bus access exception is not detected.