JPH01233643A - Data transfer controller - Google Patents

Abstract

PURPOSE:To simultaneously trace a signal sequence on an input/output connecting line and the internal sequence of a data transfer controller by starting writing when a signal state designated on the input/output connecting line between the data transfer controller and an input/output device changes and stopping the writing at a prescribed time. CONSTITUTION:While a trace memory circuit 5 updates an address according to a given clock, the circuit 5 successively writes internal signals from a data transfer control circuit 1 and signals on the input/output connecting line. On the other hand, when a timer circuit 3, which is started by an detected output from a change detecting circuit 2, gives a time-out signal to a memory control circuit 4 at a point where its time period is completed, the updating of the address and the signal writing at a trace memory circuit 5 are stopped at the point. When the change detecting circuit 2 detects a seizing signal again after that, the above-mentioned operations are repeated, and the signal sequence from next starting to data transmission and reception is written to the trace memory circuit 5. Thus, only detailed sequence information between the data transfer controller 1 and the input/output device can be written to the trace memory circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer control device, and particularly to a data transfer control device capable of accumulating trace information of signals on input/output connection lines connected to input/output devices.

[Conventional technology]

Conventionally, this type of data transfer control device has either an external trace device or a permanently built-in trace device, but in both cases, the signal line to be traced and the is connected to the memory circuit, and starts writing signals manually or by a trace start instruction from a specific external device, and when the signals on one or more signal lines meet the set conditions, the writing starts. It is supposed to stop working. Therefore, the address of the memory circuit is updated sequentially from the start of writing, and the memory is used cyclically, returning to the first address after the last address, and the latest data within the capacity remains in the memory. Further, as the write clock, a clock of the data transfer control device or a sampling period at which the data transferred to and from the input/output device can be grasped is used.

[Problem to be solved by the invention]

However, in the conventional data transfer control device described above,
When writing to the memory circuit for tracing is performed using the operating clock of the data transfer control device, the time for the data transfer sequence on the input/output connection line with the input/output device is extremely long compared to the above operating clock. Due to capacity limitations of memory circuits, only a small portion of the data on the input/output connection lines is usually left. Furthermore, if writing to the trace memory circuit is performed in accordance with the data transferred to and from the input/output device, internal signals of the data transfer control device and short crack signals on the input/output connection lines may not be written accurately. occurs. Therefore, there is a problem in that it is not possible to simultaneously store and trace the internal signal sequence of the data transfer control device and the sequence on the input/output connection line.

An object of the present invention is to synchronize the write clock of a memory circuit for tracing with the operation clock of a data transfer control device, and to start writing when a change occurs in the signal state specified on the input/output connection line with the input/output device. An object of the present invention is to provide a data transfer control device which simultaneously traces a signal sequence on an input/output connection line and an internal sequence of the data transfer control device by stopping writing at a predetermined time.

[Means to solve the problem]

A data transfer control device of the present invention is a data transfer control device that is connected to an input/output device via an input/output connection line and controls data transfer between a main storage device and the input/output device.
a trace memory circuit that writes signals on the input/output connection lines and internal signals of the data transfer control device in synchronization with the operation clock of the control device; and a trace memory circuit that detects changes in at least the control line of the input/output connection lines. a timer circuit that is activated by the detection output of the change detection means and sends a timeout output and resets when the time limit expires; and a timer circuit that starts writing in the trace memory circuit upon receiving the output of the change detection means; and a memory control circuit that receives a timer-out output from the timer circuit and stops the writing.

With the above configuration, detailed sequence information between the data transfer control device and the input/output device from the transmission and reception of the start signal to immediately after the start of transmission and reception of the data signal, and from the end of the transmission and reception of the data signal to the transmission and reception of the end control signal. Only trace data can be written to the memory circuit.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, in which a data transfer control circuit 1, which is the main body of a data transfer control device, is connected to a main memory device via a system bus, and has input ports including control lines and data lines. A case is shown in which it is connected to an input/output device via an output connection line.

This embodiment includes the above-described data transfer control circuit 1, change detection circuit 2, timer circuit 3, memory control circuit 4, and trace memory circuit 5.

The data transfer control circuit 1 is located between the main storage device and the input/output device, and performs the original control of data transfer between the two devices. The change detection circuit 2 monitors the control signal and data signal on the input/output connection line, detects a change in a preset signal, and sends a detection output to the timer circuit 3 and the memory control circuit 4.

When the timer circuit 3 receives the above detection output, it starts a timed operation, and when the preset time limit expires, it sends a timer-out output to the memory control circuit 4, and resets itself to prepare for the next timed operation. The memory control circuit 4 instructs the trace memory circuit 5 to perform a write operation from the time it receives the above detection output until the time it receives the above timeout output. During a write operation instruction from the memory control circuit 4, the trace memory circuit 5 uses the internal signals provided from the data transfer control circuit 1 and the signals on the input/output connection line as a clock for the internal operation of the data transfer control circuit 1. Update and write addresses sequentially in synchronization.

Next, proceeding with the explanation of the trace information writing operation shown in FIG. Set the time limit from the start of writing to the stop of writing. This time limit is, for example, the scheduled time from startup to the beginning of data transmission/reception. Therefore, when the change detection circuit 2 is given an operation start instruction from an external circuit (not shown) and the change detection circuit 2 detects the start signal, the memory control circuit 4 immediately instructs the trace memory circuit 5 to perform a write operation. give. The trace memory circuit 5 sequentially writes internal signals from the data transfer control circuit 1 and signals on the input/output connection line while updating the address according to the applied clock.

On the other hand, when the timer circuit 3 activated by the detection output from the change detection circuit 2 gives a timeout signal to the memory control circuit 4 at the end of the time limit, updating and writing of the address in the trace memory circuit 5 is stopped at that point. Thereafter, when the change detection circuit 2 detects the activation signal again, the above operation is repeated, and the signal sequence from the next activation to data transmission/reception is written into the trace memory circuit 5. Next, the operation of the change detection circuit 2 is stopped except for an instruction to start operation from an external circuit that has been given to the change detection circuit 2, and although not shown, the information written in the trace memory circuit 5 is written in the same way as in the conventional case. Read the contents to an external device.

In the above description of the write operation, it is assumed that the signal from the start signal to the beginning of data transmission/reception is written, but in the change detection circuit 2, for example, the data on the input/output connection line By detecting a change in the signal, writing can be started and the signal sequence for the end portion of data transmission/reception can also be written into the trace memory circuit 5.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the internal operation clock of the data transfer control device is clocked only at a specified time from the generation of a specified signal on the input/output connection line between the data transfer control device and the input/output device. Since the internal signals of this control device and the signals on the input/output connection lines are written into the trace memory in synchronization with Since it is stored efficiently, the memory capacity is small and the trace information can be easily analyzed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. 1... Data transfer control circuit, 2... Change detection circuit, 3... Timer circuit, 4...
-Memory control circuit, 5...Trace memory circuit. Agent Patent Attorney Shinju Uchihara J Ko-1-I entered the device to buy a monk once.

Claims (1)

[Claims] In a data transfer control device that is connected to an input/output device via an input/output connection line and controls data transfer between the main storage device and the input/output device, the signal on the input/output connection line and the internal information of the data transfer control device are a trace memory circuit for writing the signal in synchronization with the operating clock of the control device; a change detection means for detecting a change in the signal of at least the control line of the input/output connection lines; and a detection means for detecting the change. a timer circuit that is activated upon receiving the output, sends out a timeout output and resets upon expiration of a time limit; a timer circuit that starts writing in the trace memory circuit upon receipt of the output of the change detection means; and upon receipt of the timeout output of the timer circuit; A data transfer control device comprising: a memory control circuit for stopping the above writing.