JPH0452948A - Data transfer system for input/output controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a data transfer method in an input/output control device, and aims to reduce delays in transfer processing without interfering with processor processing. DMA data between each connected input/output control circuit, main memory, and input/output device
An input/output control device including a high-speed DMA bus for transfer and a processor for controlling a transfer state is provided with a buffer memory and a buffer memory control circuit to which each input/output control circuit and the high-speed DMA bus are connected, The two are connected via a high-speed buffer memory DMA bus, and the processor uses the data transfer path in the buffer memory control circuit when data transfer via the high-speed DMA bus is being performed between one of the input/output devices and the main memory. , if there is a request to transfer the data of the other input/output device to the main memory, the data is stored in the buffer memory, and when the data transfer completion notification is received, the stored data is transferred to the main memory via the high-speed DMA bus. It has a configuration that performs switching control to transfer data to memory.

[Industrial application field]

The present invention relates to a data transfer method using a high-speed DMA bus between an input/output device and a main memory in an input/output control device having two data transfer ports with the input/output device.

[Conventional technology]

A conventional data transfer method for an input/output control device having two data transfer ports with input/output devices is shown in FIG.

In FIG. 5, a first input/output device 51. The second input/output devices 52 each include an input/output control device 50 . Data is transferred via DMA to the main memory 64 via the system bus 66.

Here, the input/output control device 50 is the first input/output device 51
and data from the second input/output device 52 to the main memory 6
4 simultaneously, and a high-speed DMA bus 6 is used for this purpose.
Data transfer between the first input/output device 51 and the main memory 64 (first connection system) First input/output device 51- First input/output control circuit 56 - High IDMA bus 62 - System bus stator control circuit 55 -
System bus 66 - main memory 64 ■' Data transfer between second input/output device 52 and main memory 64 (second connection system) Second input/output device 52 - second input/output control circuit 57 - Buffer control circuit 58 - data buffer 59 - (after the stored data reaches a specified amount) buffer control circuit 58 -
Low-speed DMA bus 63 - Internal data bus 60 - System bus data control circuit 55 - System bus 66 - Main memory 6
4, the data of each input/output device is transferred by DMA.

In addition, each input/output control circuit 56゜5 of the input/output control device 50
7, memory, etc. are controlled by a main processor 53, and an internal address bus 61 and a system bus 66
are both connected to the system bus control circuit 54.

[Problem to be solved by the invention]

As described above, in the conventional DMA transfer method for an input/output control device having two systems of data transfer ports with input/output devices, the internal data bus 60 is used when transferring data in the second connection system.

Therefore, this DMA transfer, which originally uses the low-speed DMA bus 63, is executed at regular intervals so as not to interfere with the processing performed by the main processor 530.
There is a problem in that the DMA transfer processing in this connection system is delayed, and the performance of the entire system is limited by the processing time in the connection system.

Therefore, in the present invention, an input/output control device is provided with a large-capacity buffer memory and a buffer memory control circuit connected to each input/output control circuit and a high-speed DMA bus, and both are connected by a high-speed buffer memory U DMA bus. At the same time,
The main processor controls the buffer memory control circuit to transfer data from the other input/output device to the main memory when one input/output device is transferring data to and from the main memory using a high-speed DMA bus. If there is a request to transfer the data, write it in a high-speed buffer memo! 7 DMA bus, and when a notification of completion of the DMA transfer is received from one of the input/output control devices, the data stored in the buffer memory is transferred to the main memory via the high-speed DMA bus. DMA transfer between each input/output device and the main memory is performed using a high-speed DMA bus without using an internal data bus, reducing delays in transfer processing without interfering with processor processing. The purpose is to

[Measures to solve problems]

FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, reference numeral 1 denotes an input/output control device to which a first input/output device 9, a second input/output device 10, and a system bus 13 are connected.

A main processor 2 controls the buffer memory control circuit 4 and the like.

3 is a large-capacity buffer memory, and when data is transferred between one input/output device and the main memory 12 using the high-speed DMA bus 8, data is transferred from the other input/output device to the main memory 12. If there is a data transfer request, the data is stored therein, and it is also used as a data buffer from the main memory 12. For example, a large-capacity DRAM for video signals is used.

4 is a buffer memory control circuit which receives commands from the main processor 2 and transfers data between the high speed buffer memory DMA bus 7, the high speed DMA bus 8 and the input/output control circuits 5 and 6 in the buffer memory control circuit. It performs path switching control and also performs address selection control of the buffer memory 3.

Reference numeral 5 denotes a first input/output control circuit, which controls input/output processing of the first input/output device 9.

Reference numeral 6 denotes a second input/output control circuit, which controls input/output processing of the second input/output device 10.

7 is a high-speed buffer memo! IDMA bus, which connects a large-capacity buffer memory 3 and a buffer memory control circuit 4.

A high-speed DMA bus 8 connects the system bus 13 and the buffer memory control circuit 4.

9 is a first input/output device, and lO is a second input/output device.

11 is a CPU, which sends input/output commands to the input/output control device 1 via the system bus 13.

A main memory 12 is connected to the input/output control device 1 and the CPU 11 via a system bus 13.

13 is a system bus, CPU II, main memory 1
2 and an input/output control device 1 are connected.

Here, the input/output control device 1 is activated by the input/output command from the CPU II. When there is a request for simultaneous data transfer between the second input/output devices 9 and 10 and the main memory 12, the main processor 2
For example, connect the high-speed DMA bus 8 and the first input/output control circuit 5, confirm that the high-speed DMA bus 8 is in use, and write the high-speed buffer memo! l Issues a command to connect the DMA bus 7 and the second input/output control circuit 6.

As a result, DMA transfer of data is performed between the first input/output device 9 and the main memory 12 via the high-speed DMA bus 8, and data from the second input/output device is transferred to the high-speed buffer memory 12. The signal is stored in the large capacity buffer memory 3 via the IDMA bus 7. When the DMA transfer via the high-speed DMA bus 8 is completed, the first input/output control circuit 5 interrupts and notifies the main processor 2 that the rDMA transfer is complete. Upon receiving this notification, the main processor 2 instructs the buffer memory control circuit 4 to confirm that the high-speed DMA bus 8 is unused and to switch the data transfer path. teeth,
Is the data stored in buffer memory 3 transferred to the high-speed buffer memory DMA bus? and a buffer memory control circuit 4 for transmitting data to the main memory 12 via a high-speed DMA bus 8.
Switch the data transfer path inside.

[Effect]

The first aspect of the present invention. The processing procedure for DMA transfer between the second input/output device 9.10 and the main memory 12 is as shown in FIG.

That is, ■ The main processor 2 determines whether a DMA transfer request is issued between the input/output device 9.10 and the main memory 12, and if r YBSJ, proceeds to step ■;
If "NO", this judgment is repeated.

■ Check whether the flag indicating the usage status of high-speed DMA bus 8 is in the high state, and select r YESJ.
If ``NO'', proceed to step ■; if ``NO'', proceed to step ■.

The data of the input/output device (not connected to the high-speed DMA bus 8) is stored in the buffer memory 3 via the high-speed buffer memory DMA bus 7, and the process proceeds to the next step.

■ Data transfer between the main memory 12 and the high-speed DMA bus 8
It is determined whether there is an interrupt notification of "end of rDMA transfer" from the input/output control circuit of the input/output device that is performing MA transfer, and if "rYIEs", proceed to the next step; if "NO", this judgment is made. repeat. Note that instead of the above-mentioned interrupt notification, it may be checked whether the flag indicating the usage state of the high-speed DMA bus 8 is in the high state.

(2) The data transfer path in the buffer memory control circuit 4 is switched so that it is connected to the buffer memory 3 - high speed buffer memory D (1) MA bus 7 - high speed DMA bus 8, and the process proceeds to step (2).

■ Connect the data transfer path in the buffer memory control circuit 4 to the high-speed DMA bus 8- (to which DMA transfer is to be performed).
Switch so that it is connected to the input/output control circuit and proceed to the next step.

(2) Performs DMA transfer of data with the main memory 12 via the high-speed DMA bus 8.

It looks like this.

Note that the above data transfer process applies not only to DMA transfer from the input/output device 9-10 to the main memory 12, but also for DMA transfer from the main memory 12 to one input/output device and the other input/output device. It can also be used when DMA transfer from the device to the main memory 12 is performed simultaneously.

〔Example〕

The present invention will be described in detail with reference to FIGS. 3 and 4.

FIG. 3 is an explanatory diagram showing an embodiment of the input/output control device,
First input/output device 51. The second input/output devices 52 include the input/output control devices 30 . Data is transferred via DMA to the main memory 64 via the system bus 66.

The conventional input/output control device 50 shown in FIG. 5 includes a large capacity buffer memory 31 and each input/output control circuit 3.
6.37 # and the buffer memory control circuit 32 to which the high-speed DMA bus 62 is connected are provided, and both are connected by the high-speed buffer memory DMA bus 33. In the buffer memory control circuit 32, each input/output control circuit 36 .37 and each bus (high-speed buffer memory DMA bus 33, high-speed DMA bus 62, low-speed DMA bus 63). ・Providing a flag indicating the use status of the high-speed DMA bus 62, for example, each input/output device 51 ．．
52 and the main memory 64 at the same time, one of the input/output devices is connected to the high-speed DMA bus 62.
When the high-speed buffer memory IIJ DMA bus 33 is used first and the flag indicates the busy state, the buffer memory control circuit 32 confirms that the high-speed buffer memory IIJ DMA bus 33 is in an unused state and transfers the data transferred from the other input/output device. The stored data is once stored in the buffer memory 31, and as soon as the use of the high-speed DMA bus 62 of one input/output device is finished, the stored data is transferred from the buffer memory 31 to the high-speed buffer memory DMA bus 3.
3. D to the main memory 64 via the high-speed DMA bus 62
They are different in terms of MA transfer, etc.

Therefore, in the input/output control device 30 of the present invention,
Conventional ■' I/O control circuit 36, 37 - high-speed DMA bus 62 -
System bus data control circuit 55-system bus 66-
Main memory 64 ■'Input/output control circuit 36.37 - software memory 31 -
Low speed DMA bus 63 - Internal data bus 60 - Low speed DMA
In addition to the system bus 63 - system bus data control circuit 55 - system bus 66 - main memory 64,
High-speed buffer memory DMA bus 33-high-speed DMA bus 6
2-System bus data control circuit 55-System bus 6
6-Main memory 64 data transfer path will be formed. Note that 34 is an address bus to the buffer memory 31.

FIG. 4 is an explanatory diagram showing an embodiment of the buffer memory control circuit 32.

Here, the buffer memory 31 and the first input/output control circuit 3
6. Transceivers 41, 42 are provided on data transfer paths connecting each of the second input/output control circuits 37, and the system bus data control circuit 55 and the first input/output control circuit 36. Transceivers 43 and 44 are provided on the data transfer paths connecting each of the second input/output control circuits 37, and transceivers 45 and 45 are provided on the data transfer paths connecting the buffer memory 31 and the system bus data control circuit 55. is provided at 1°, and the transceivers 41 to 4
5 is controlled on/off by a BCR (bus control register) 46, and the direction of data transfer is controlled by a BCR (bus control register) 46.
It is controlled by CR47. In addition, the high-speed DMA bus 62
．． Low speed DMA bus 63. BSR (
A bus status register) 48 is provided. Each of the above registers is composed of, for example, 8 bits, and in the initial state, all bits are set to "0", and the bits corresponding to the transceiver to be enabled and the bus in use are set to "]". There is.

Further, a buffer memory control unit 49 is provided that controls addresses and sequence operations in the buffer memory 31 for storing data 15 or for accessing the buffer memory when retrieving stored data.

For example, the first one is capable of high-speed data transfer. The processing procedure of each part when both the second input/output devices transfer data to the main memory 64 is as follows.

That is, (a) the input/output control device 30 receives input/output commands from the CPU 65 via the system bus 66, thereby transferring data between each input/output device 51, 52 and the main memory 64.
An attempt is made to perform MA transfer. At this time, it is assumed that the first input/output device 51 uses the high-speed DMA bus 62, for example.

(b) Prior to DMA transfer, the main processor 35 sets predetermined bits in the BCRs 46 and 47 to "1" to turn on the transceivers 42 and 43, and also connects the high-speed DMA bus 62 from the first input/output device 51. data transfer to the system bus data control circuit 55 via the system bus, and high-speed buffer completion memo from the second input/output device 52! The transfer direction of the BCRs 46 and 47 is controlled so that data can be transferred to the buffer memory 31 via the JDMA bus 33.

(C) The data read from the first input/output device 51 is transferred to the main memory 64 via the high-speed DMA bus 62.
The data transferred and read from the second input/output device 52 is stored in the buffer memory 31 via the high speed buffer memory DMA bus 33.

(6) When the data transfer of each system is completed, the input/output control circuits 36 and 37 respectively notify the main processor 35 of the termination side fullness.

At this time, if the amount of data transferred from each input/output device 51, 52 is within the range, the data transfer to the buffer memory 31 is completed first. DM of data between the input/output device 51 and the main memory 64 using the high-speed DMA bus 62
When the A transfer ends, the first input/output control circuit 36 generates an end interrupt, and the main processor t351 that receives this interrupt
t, turns on the transceiver 45 by controlling the bit settings of BCR 46 and 47, and connects the path of buffer memory 31 - high speed buffer memory DMA bus 33 - high speed DMA bus 62 - system bus data control circuit 55 - system bus 66 - main memory 64. Performs DMA transfer.

Such data processing is being carried out.

〔Effect of the invention〕

The present invention provides an input/output control device with a large-capacity buffer memory and a buffer memory control circuit, connects the two with a high-speed buffer memory DMA bus, and allows the main processor to control the data transfer path in the buffer memory control circuit.
When data is being DMA transferred between one input/output device and the main memory using a high-speed DMA bus, if there is a request to transfer data from the other input/output device to the main memory, the data is transferred to the main memory. stored in the buffer memory, and also the DM
When a notification of the completion of A transfer is received from one of the input/output control devices, switching control is performed to transfer the data stored in the buffer memory to the main memory via the high-speed buffer memory DMA bus, high-speed DMA bus, etc. , the configuration allows DMA transfer of data between each input/output device and the main memory without using the internal data bus, so it does not interfere with the processing of the main processor.
DMA transfer of data between multiple input/output devices and main memory can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is an explanatory diagram showing the processing procedure of DMA transfer between the input/output device and the main memory of the present invention, and FIG. 3 is an explanatory diagram showing an embodiment of the data transfer method of the present invention. ,
FIG. 4 is an explanatory diagram showing an embodiment of the buffer memory control circuit of the present invention, and FIG. 5 is an explanatory diagram showing a conventional data transfer system. In FIG. 1, 1... Input/output control device 2... Main processor 3... Large capacity buffer memory 4... Buffer memory control circuit 5... First input/output control circuit 6...・Second input/output control circuit 7...high-speed buffer memo! l DMA bus 8...High-speed DMA bus 9...First input/output device 10...Second input/output device 12...Main memory 13...System bus Patent applicant BFN Corporation

Claims (2)

[Claims] (1) A first input/output control circuit and a second input/output control circuit that are connected to the first input/output device and the second input/output device and each controls the input/output devices, and a main input/output control circuit. In an input/output control device comprising a memory, a high-speed DMA bus for DMA transfer of data between the input/output devices, and a processor for controlling the data transfer state, the input/output control device includes a large-capacity buffer memory. and a buffer memory control circuit to which each of the input/output control circuits and the high-speed DMA bus are connected, the buffer memory and the buffer memory control circuit are connected via the high-speed buffer memory DMA bus, and the processor , one of the first and second input/output devices is connected to the main memory via the high-speed DMA bus.
During MA transfer, if there is a request to transfer data from the other of the first and second input/output devices to the main memory, the data is stored in the buffer memory via the high speed buffer memory DMA bus. , when a notification of completion of the DMA transfer is received from the first input/output control device, the data stored in the buffer memory is DMA-transferred to the main memory via the high-speed buffer memory DMA bus and the high-speed DMA bus. switching and controlling a data transfer path in the buffer memory control circuit so as to transfer data between each of the input/output devices and the main memory without using an internal data bus to which the processor is connected; A data transfer method in an input/output control device, characterized in that DMA transfer is performed using a high-speed DMA bus. (2) A bus status register that reflects the usage status of the high-speed buffer memory DMA bus and the high-speed DMA bus, and between the first input/output control circuit, the second input/output control circuit, the high-speed buffer memory DMA bus, and the high-speed DMA bus A bus control register is provided for switching and controlling the data transfer path in the buffer memory control circuit, and the processor checks the state of the bus status register and controls the bus control register based on the result. 2. A data transfer system in an input/output control device according to claim 1, wherein bits are set.