JPH01236331A - Error detecting system - Google Patents

Abstract

PURPOSE:To diagnose a faulty point where a data changing trouble, etc., takes place by reporting the abnormality of a selection control signal which controls the selection of data to be stored in a register as a parity error of the register when the abnormality is detected. CONSTITUTION:Presence/absence of abnormality in a control signal producing section 7 is detected by performing AND operation on inverted signals 108 which are produced by inverting selection controlling signals 104 from the section 7 at a NOT gate 5 and condition signals 103 and 113 at an AND gate 6. When abnormality is detected, a parity error signal 110 from an OR gate 4, at which the OR with the output signal 107 of a parity check circuit 3 is taken, becomes '1'. Therefore, where a fault occurs at a register or at the control signal producing section 7 can be discriminated when the calculated result from the AND gate is checked.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error detection method, and in particular to an error detection system for detecting errors in data registers that can cause data corruption in computers that use parity checks to detect irregularities in data stored in data registers during operation. Error Detection Methods for Detecting Illegal Control Signals Conventionally, error detection methods for signal lines include methods using various code logics such as parity codes, and methods that detect data mismatches by comparing data.

However, if checking the normality of the control signals around the data register also includes checking the normality of the control signal generation section, the amount of hardware for the code generation logic and error detection logic increases, and the amount of hardware required for the data register increases. Because the failure rate of the control signal generation unit is lower than the failure rate of the control signal generation unit itself, or because the cost increases due to an increase in the amount of hardware, it is not implemented in systems other than some systems where reliability is particularly required. The current situation is that there is no such thing.

Also, if control signals are sent across packages that make up a computer,
Since there are many failures at the inter-package interface, the reliability of the device is improved by detecting only errors at the inter-package interface.

That is, in this case, a parity is generated in the package on the sending side of the control signal, and the parity is checked in the package on the receiving side to detect a failure in the interface section between the bag gauges. However, this method cannot detect abnormalities in the main component of the control signal itself.

In such conventional error detection methods, a parity check circuit is provided for the data read from the data register due to failure rate, amount of hardware, cost, etc., but a switching circuit for switching the set data to the data register is provided. No error detection circuit is provided for the control signal. Therefore, even if incorrect data is selected and set in the data register due to an incorrect control signal in the switching circuit, there is no way to detect that incorrect data has been set in the data register due to an incorrect control signal. There's a problem.

Also, when control signals cross between packages,
Although it is possible to detect errors in the inter-package interface by parity checking, there is a problem in that it is not possible to detect an abnormality in the control signal generation section that generates the control signal.

Furthermore, if incorrect data is set in the data register due to an incorrect control signal of the switching circuit, the parity check performed when reading data from the data register will detect the error if the parity of the incorrect data is correct. There are cases where it is not possible to do so, and there is a problem that data may be garbled.

In the case of data corruption like this, it is extremely difficult to diagnose the location of the failure.

Yu J! Similar to this, the present invention was made in order to eliminate the problems of the conventional ones as described above, and the purpose of data conversion is to provide an error detection method that can easily diagnose the location of a failure in the event of a failure. do.

The error detection method according to the present invention is an error detection method for an information processing device in which one of a plurality of pieces of data is selected according to a selection control signal and stored in a register, and the comprising a detection means for detecting an abnormality, and when the detection means detects an abnormality in the selection control signal,
The present invention is characterized in that the abnormality is reported as a parity error in the register.

K1 fake Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. It is composed of a gate 5, an AND gate 6, and a control signal generation section 7.

During normal operation, when the control signal generation section 7 receives the condition signal 103, it generates the selection control signal 104 and outputs it to the switching circuit 1. The switching circuit 1 switches between data 101 and data 102 under the control of a selection control signal 104 from the control signal generating section 7 and sends it to the register 2 as set data 105.

The switching circuit 1 normally receives a selection control signal 104 of logic “0”.
is input, and data 101 is set data 105
The condition signal 103 is sent to register 2 as
When becomes the logic "1", the control signal generation unit 7 takes the logic of multiple factors using this as a trigger, and the control signal generation unit 7
When the selection control signal 104 from the switch circuit 1 becomes logic "1", the data 102 is selected for the first time in the switching circuit 1, and the data 102 is transferred to the register 2 as the set data 105.
sent to.

The output data 106 from the register 2 is checked for abnormality by the parity check circuit 3. If the output data 106 is normal, the output signal 107 from the parity check circuit 3 is logic "0", indicating that the output data 106 is abnormal. If there is, output signal 1 from parity check circuit 3
07 becomes logic "1".

When the output signal 107 from the parity check circuit 1i 183 becomes a logic "1", a logic "1" is outputted to the outside as a parity error signal 110 via the OR gate 4, and the detection of a parity error is reported.

On the other hand, during the above operation, the selection control signal 104 from the control signal generation unit 7 is inverted by the not gate 5 and the inverted signal 10
8 and is output to the AND gate 6.

The AND gate 6 performs an AND operation between the condition signal 103 and the inverted signal 108, and outputs the operation result signal 109 to the OR gate 4 and the outside.

When the control signal generation section 7 is operating normally, a logic "0" is output as the operation result signal 109 from the AND gate 6 which reports the abnormality of the control signal generation section 7.

Next, if an abnormality occurs in the control signal generation unit 7 and the selection control signal 104 is not issued, the selection control signal 104 is not issued even though logic “1” is input to the control signal generation unit 7 as the condition signal 103. The signal 104 does not become a logic “1”;
Since the inverted signal 108 from the NOT gate 5 becomes logic "1", the operation result signal 109 from the AND gate 6 is outputted as logic "1", indicating that the control signal generating section 7 is abnormal.

The operation result signal 109 from the AND gate 6 is logically summed with the output signal 107 from the parity check circuit 3 in the OR gate 4, and when an abnormality in the control signal generation 7 is detected, the parity of the register 2 is Reported as an error.

The parity error signal 110 from the OR gate 4 is logic “
1'', by looking at the operation result signal 109 from the AND gate 6, it can be determined whether the fault is in the register 2 or in the control signal generating section 7.

FIG. 2 is a block diagram showing a specific example of the control signal generating section 7 shown in FIG. 1. In the figure, a reset control register 71 that is provided in the control signal generation unit 7 and controls the initial settings of each register (not shown) in the device, and a flip-flop 8 that holds a reset signal 112 are provided, and the switching circuit 1 1 except that the initial setting data 111 is input to
It has the same configuration as the figure, and the same components as in FIG. 1 are given the same reference numerals.

The reset control register 71 inside the control signal generator 7 is reset when the reset signal 112 is at logic "1". At this time, bit 0 of the reset control register 71 becomes logic "0".

When bit 0 of the reset control register 71 becomes logic "0", the selection control signal 104 outputted by inverting the value of bit 0 becomes logic "1", and this selection control signal 104 causes the switching circuit 1 is initial setting data 111
Select and output to register 2. The register 2 is initialized by setting the initial setting data 111 from the switching circuit 1. Parity checking of output data 106 from register 2 is similar to the embodiment of the present invention shown in FIG.

The condition signal 113 outputted from the flip-flop 8 is a signal equivalent to the reset signal 112, and its timing is equal to the timing of the selection control signal 104 outputted from the reset control register 71.

That is, when the reset signal 112 of logic "1" is input to the control signal generation section 7, the selection control signal 104 is outputted, and the selection control signal 104 causes the switching circuit 1i'll
is controlled. At this time, the condition signal 113 from the flip-flop 8 is output to the AND gate 6.

Therefore, by performing an AND operation between the inverted signal 108 from the NOT gate 5 and the condition signal 113 from the flip-flop 8 using the AND gate 6, the presence or absence of an abnormality in the control signal generation section 7 is detected.

In this way, the selection control signal 10 from the control signal generation section 7
4 is inverted by the NOT gate 5, and the condition signals 103 and 113 are logically ANDed by the AND gate 6 to detect whether or not there is an abnormality in the control signal generation section 7. When an abnormality is detected, the OR gate is activated. 4 as a parity error signal 110, it is possible to detect a failure in normally setting data to the register 2 due to an abnormality occurring in the control signal generation unit 7, and data conversion is performed at the time of failure. It is possible to easily diagnose failure points such as:

Kuhada Gozu A As explained above, according to the present invention, when an abnormality is detected in the selection control signal for selecting data to be stored in a register, this abnormality is reported as a parity error in the register. By doing so, data conversion has the effect of making it easier to diagnose the location of a failure in the event of a failure.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing a specific example of the control signal generation section of FIG. 1. Explanation of symbols of main parts 1...Switching circuit 2...Register 4...OR gate 5...Not gate 6...And gate 7・・・・・・Control signal generation section

Claims (1)

[Claims] (1) An error detection method for an information processing device in which one of a plurality of data is selected according to a selection control signal and stored in a register, comprising a detection means for detecting an abnormality in the selection control signal, An error detection method characterized in that when an abnormality in the selection control signal is detected by the detection means, the abnormality is reported as a parity error in the register.