JPH012365A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, particularly an LSI using silicon, in which a direct contact between polycrystalline silicon and aluminum is made on a thin oxide film. It can be used as a method.

2. Description of the Related Art In recent years, as LSIs have become more highly integrated and densely packed, the device structures used have also become finer. This is particularly noticeable in MO8LSIs using silicon. For example, M
Taking the gate oxide film of an OS transistor as an example, 198
It was 70nm around 1984, 40nm in 1984, and now 20nm, and for special applications it has become 10nm, which has significantly increased to 3. In addition, polycrystalline silicon (hereinafter abbreviated as Po1ySi) was widely used for the gate electrode on the oxide film, but recently, high-melting point metals and silicide, which is a compound of high-melting point metals and silicon, have also been used for high-speed MO8LSr. A cross-sectional view of the structure of a standard MOS transistor is shown in FIG.

A thin gate oxide film 3 and a thick field oxide film 2 are formed on a silicon substrate 1, and a low-resistance PolySi gate electrode 6 is further patterned over both. The region of thin oxide becomes the active region of the MOS transistor, and the region of thick oxide becomes the passive region and the isolation of the active region to the transistor. However, this figure does not show the source or drain of the transistor.

The gate electrode 6 of this MOS transistor is normally connected to an external wiring through an aluminum wiring M9 from a contact portion 8 of an interlayer 11i7. At this time, the above-mentioned contact portion 8 is normally formed on the Po1ySi6 on the field oxide film 2. This is because the smaller the capacitance between the aluminum wiring part covering the contact and the underlying silicon, the faster the MO3LSI speed will be.
This is because the wiring is cut in the part where the oxide film between the two is thicker.

However, as the degree of integration increases, Po1ySi is often used as wiring, and the resistance of the wiring becomes impossible to ignore.
Even in the o 1 ySi gate wiring, if it is pulled around by 500 microns with a width of 2 microns, the resistance will be as high as 5Ω. Therefore, in order to lower the resistance, it is necessary to line it with a low-resistance metal such as aluminum. In other words, it is necessary to deposit aluminum directly on the PoIyS, and not only on the field oxide film 2 as in the conventional method (but also on the gate oxide film 3 for higher density). Unless a direct contact of i-aluminum is provided, the resistance will be from below.Of course, without using Po1ySi as the gate electrode,
If a silicide compound or a high melting point metal is used, the resistance will be reduced by 1/'5, but problems remain in the manufacturing method.

Therefore, in the conventional Po1ySi wiring process, after forming a thick field oxide 1112 and a thin gate oxide film 3, Po1ySi, which serves both as a gate electrode and a wiring, is deposited, and impurities are introduced by thermal diffusion. Now, this thermal diffusion method involves heating the silicon substrate with the above-mentioned POlysi in a high-temperature electric furnace at about 900°C.
By flowing carrier gas and oxygen gas over a diffusion source such as OCl2) or boron tribromide (BBr3),
Glass layers of P (phosphorus) and B (boron) are formed on the film, and a large amount of P or B is doped therein. A method is used in which this non-nium glass layer of P or B is removed with hydrofluoric acid, and then an interlayer insulating film 7 is deposited, a portion is opened with diluted acid, and an aluminum film 9 is deposited. actual MO
Although the manufacturing process of 3LSI is more complicated, only the parts related to the present invention have been described here.

Problems to be Solved by the Invention However, as described above, as the gate oxide film becomes thinner, a new problem arises, which manifests itself as poor breakdown voltage of the gate oxide film. In other words, Po
It has been found that the yield of MO8LSI is extremely reduced by using IySi-aluminum direct contacts. In other words, as shown in FIG. 3, a low-resistance Po
When examining the oxide film breakdown voltage of the 1ySi6° and aluminum film 9 deposited, as shown in FIG. 4, many breakdown voltage failures occur. This is particularly noticeable when the oxide film thickness is 50 nm or less.

The above problem seems to occur for the following reasons. That is, P
When olyS i is deposited on an oxide film, many small grains (crystal grain boundaries) are generated, and the glass layer penetrates into the oxide film along the grain boundaries due to thermal diffusion in the next step. In the process of removing the next glass layer, the underlying oxide film is thinly etched, and if aluminum comes there, it is expected that the reduced oxide film thickness will cause breakdown voltage failure.Furthermore, Po1
It is also said that abnormal diffusion of aluminum occurs due to the stress generated due to the difference in thermal expansion coefficient between the two-layer structure of ySi-aluminum. In particular, Po has a large number of irregular grain boundaries.
Localized stresses appear to occur in the case of l yS i-aluminum. This is because a single layer film of a polysilicon gate or an aluminum gate does not cause any deterioration in breakdown voltage. In either case, it is closely related to the deposition state of Po1ySi. In other words, the existence of grain boundaries is of great significance, and it is judged that they have an adverse effect because impurity lumps are trapped during thermal diffusion. Usually, Po1ySi is deposited by thermal decomposition of SiH4 gas in a reduced pressure atmosphere at around 600° C., and since the base is an oxide film, grain boundaries are sure to occur. Although it can be deposited in an amorphous form at a lower temperature, grain boundaries will grow if it is heat treated again during the next step of thermal diffusion.

The present invention has been made in view of the above-mentioned problems.
It is an object of the present invention to provide a semiconductor manufacturing method that can suppress the occurrence of grain boundaries in 1ySi as much as possible, improve uniformity during thermal diffusion, and reduce breakdown voltage defects of gate oxide films.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention includes a step of implanting Si ions after depositing Po1ySi and then performing thermal diffusion at high temperatures.

Effect The present invention uses the above-mentioned structure to reduce the grain boundaries of Po1ySi, transform it into Po1ySi with high density and good crystallinity, and to form PoIySi with a uniform structure by thermal diffusion in the next step.
Since yS i is maintained, the adhesion with aluminum is improved, no local stress is observed, and the effect on the gate oxide film is extremely small (and the oxide film breakdown voltage can be improved). Become.

Embodiment FIG. 1 is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. A thick field oxide film 2 and a thin gate oxide film 3 are formed on a silicon substrate 1. For this purpose, a generally well-known selective oxidation method may be used.

Usually, the thickness of each thermal oxidation film is about 500 nm and 20 nm. Next, 300 nm was applied to the entire surface by low pressure CVD method.
of Polysi4 is deposited. Deposition temperature is 600℃
Utilizes thermal decomposition of iH4 gas. After that, Fig. 1(b)
Silicon (Si'') ions are implanted as shown in FIG.

5 is a Po1ySi@ region into which Si ions are implanted.

Accelerating voltage is 25Kev to 100Kev, injection amount is 1
E15/cwt or higher is desirable. On the other hand, even if the injection amount is increased further, the effects described below will only gradually increase.

After that, the silicon substrate was inserted into an electric furnace kept at 900°C, and phosphorous glass was deposited on the Po1ySi by using phosphorous oxychloride (POCl2) as a diffusion source, flowing nitrogen gas as a carrier gas, and oxygen scum as an oxidizing agent. and introduce high concentrations of phosphorus. The sheet resistance at that time is 2
It is about 5Ω/mouth. After removing the resulting phosphor glass layer of about 5 nm with hydrofluoric acid, this low resistance Po1ySi6 is formed as a predetermined pattern of a gate or wiring (FIG. 1C), and a glabella insulating film 7 is deposited. (Figure 1 d) Normal CV
It is deposited to a thickness of 500 nm or more using the D method, and then heat-treated and baked. Thereafter, as shown in FIG. 1(e), a predetermined contact window 8 is opened in the Po1ySi6 on the thin gate oxide film using photolithography and etching steps. Subsequently, aluminum wiring 9 is formed. The above is a simple process flow, and the discussion centered on the connection of PoIySic NiAluminum. As in the present invention, P
By implanting Si ions into o1ySi, grain boundaries can be eliminated and recrystallization due to heat treatment can be prevented. In addition, since it is homogeneous Po1ySi,
Diffusion is also uniform, and the phosphorus glass layer adheres only to the surface, without local penetration. FIG. 5 shows an example of an improvement in breakdown voltage using the present invention with the same oxide film thickness and gate area as the test amount shown in FIG. 4. Same as the conventional structure in Fig. 4<
, which is a direct stack of Po1ySi and aluminum, and shows clear improvement in characteristics for low electric fields.

In this embodiment, the contact portion is formed only on PolySi on a thin gate oxide film, but of course there is no problem even on a thick field oxide film. In addition, the contact part is also very large, making it suitable for most poly
Aluminum may be placed on the Si. Furthermore, in addition to aluminum, aluminum with silicon, molybdenum (Mo), tungsten (W), titanium (Ti
), cobalt (Co)1. Alternatively, silicide compounds thereof may be used.

Effects of the Invention As is clear from the above explanation, the present invention
By ion-implanting silicon into i, the crystal grain boundaries are reduced, resulting in a more uniform and high-quality PolySi film, and even after heat treatment, the P film remains uniform.

It is clear that IySi can be maintained. Therefore, Po
This makes it possible to avoid deterioration in breakdown voltage of the thin oxide film caused by the I yS i-aluminum double layer film, which in turn leads to higher integration and improved yield of MO8LSI.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of the process flow of an embodiment of the present invention, Fig. 2 is a cross-sectional view of the structure according to the conventional method, Fig. 3 is a cross-sectional view of the MO8 structure in which the oxide film breakdown voltage was measured, and Fig. 4 is An example of the distribution of oxide film breakdown voltage in the conventional method is shown, the vertical axis is the number of defects, and the horizontal axis is the electric field strength when a current of 1 nA flows through a 1 cm gate electrode. FIG. 3 is a diagram showing an example of breakdown voltage distribution of an MO8 structure according to an example of the invention. 1... Silicon substrate, 3... Gate oxide film, 6...
Book Po1ySi, 9... Aluminum wiring. Name of agent: Patent attorney Toshio Nakao and 1 other person! 1 Figure 1 Figure 2 Figure 3? Figure 4 Figure 5

Claims (3)

[Claims] (1) A step of forming a thick insulating film and a thin insulating film on a semiconductor substrate, a step of forming polycrystalline silicon on the insulating film, a step of implanting silicon ions into the polycrystalline silicon film, a step of introducing phosphorus or boron into the crystalline silicon film by thermal diffusion; a step of forming the polycrystalline silicon film into a predetermined pattern; a step of forming an interlayer insulating film on the polycrystalline silicon film; A method for manufacturing a semiconductor device, comprising the steps of forming a predetermined contact pattern on an insulating film and removing an unnecessary interlayer insulating film, and forming a thin metal film to cover the contact portion. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the contact portion is located on polycrystalline silicon on an insulating film that necessarily includes a thin insulating film. (3) Thin insulating film is 40 nm or less, silicon ion implantation amount is 1E15/cm^2 or more, thermal diffusion is 800°C or more,
The metal thin film is AL, AL containing silicon, or W,
Claim 1, characterized in that it is a high melting point metal such as Ti, Mo, or Co, or a silicide compound thereof.
Or the method for manufacturing a semiconductor device according to item 2.