JPH0124444B2 - - Google Patents
Info
- Publication number
- JPH0124444B2 JPH0124444B2 JP285883A JP285883A JPH0124444B2 JP H0124444 B2 JPH0124444 B2 JP H0124444B2 JP 285883 A JP285883 A JP 285883A JP 285883 A JP285883 A JP 285883A JP H0124444 B2 JPH0124444 B2 JP H0124444B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- time constant
- output
- variable
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000009499 grossing Methods 0.000 description 29
- 238000010586 diagram Methods 0.000 description 5
- 230000001052 transient effect Effects 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3005—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
【発明の詳細な説明】
(技術分野)
本発明は信号の包絡線成分による混変調が小さ
く、信号のレベル変動に対して速い応答速度をも
つ自動利得制御回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an automatic gain control circuit that has low cross-modulation due to signal envelope components and has a fast response speed to signal level fluctuations.
(従来技術)
従来のAGC回路を第1図に示す。第1図にお
いて11は信号入力端子、13は整流回路、14
は平滑回路、12は平滑回路14の出力により利
得が制御される可変利得回路、15は可変利得回
路12の出力の直流成分を得る出力端子である。
可変利得回路12の出力が整流回路13、平滑回
路14を介して可変利得回路12自身の制御入力
にもどることにより負帰還制御ループが形成され
て自動利得制御回路(AGC)となつている。(Prior Art) A conventional AGC circuit is shown in Fig. 1. In FIG. 1, 11 is a signal input terminal, 13 is a rectifier circuit, and 14 is a signal input terminal.
1 is a smoothing circuit, 12 is a variable gain circuit whose gain is controlled by the output of the smoothing circuit 14, and 15 is an output terminal for obtaining the DC component of the output of the variable gain circuit 12.
The output of the variable gain circuit 12 is returned to the control input of the variable gain circuit 12 itself via the rectifier circuit 13 and the smoothing circuit 14, thereby forming a negative feedback control loop to form an automatic gain control circuit (AGC).
第2図は第1図にAGC回路の各部における信
号波形を示し、第2図aは信号入力端子11にお
ける入力信号波形、第2図bは平滑回路14の出
力の信号波形、第2図cは出力端子15のAGC
出力信号波形を示す。従来実施例の場合、入力信
号の包絡線成分による混変調を小さくする為、平
滑回路14の時定数を大きくし、可変利得回路1
2への負帰還制御信号に包絡線成分が包まれない
ようにしていた。その為、入力信号に平滑回路の
時定数に対して極端に速い時定数のステツプ的な
レベル変化が発生した時、AGC出力は第2図に
示すように平滑回路14の時定数による長い時間
の過渡応答が発生することとなり、エラーとなる
時間が長くなる欠点を有していた。 Figure 2 shows the signal waveforms in each part of the AGC circuit in Figure 1, Figure 2a shows the input signal waveform at the signal input terminal 11, Figure 2b shows the signal waveform at the output of the smoothing circuit 14, and Figure 2c is the AGC of output terminal 15
Shows the output signal waveform. In the case of the conventional embodiment, in order to reduce cross-modulation due to the envelope component of the input signal, the time constant of the smoothing circuit 14 is increased, and the variable gain circuit 1
The envelope component was prevented from being wrapped in the negative feedback control signal to 2. Therefore, when a step level change occurs in the input signal with an extremely fast time constant compared to the time constant of the smoothing circuit, the AGC output will change over a long period of time due to the time constant of the smoothing circuit 14, as shown in Figure 2. This has the disadvantage that a transient response occurs and the time required for an error to occur becomes longer.
(発明の目的)
本発明は上記欠点を除去する為に平滑回路の時
定数を入力レベルのステツプ的な変化時に自動的
に切替制御して過渡応答を最小限にするものであ
り、以下詳細に説明する。(Object of the Invention) In order to eliminate the above-mentioned drawbacks, the present invention automatically switches and controls the time constant of the smoothing circuit when the input level changes stepwise to minimize the transient response. explain.
(発明の構成)
本発明は入出力利得を外部制御により可変とす
る可変利得回路と、該可変利得回路の出力を絶対
値化する絶対値回路と、スイツチにより第1の時
定数と第2の時定数に切替えでき前記絶対値回路
の出力を平滑化して前記可変利得回路を制御する
時定数可変型積分回路と、第3の時定数をもち前
記絶対値回路の出力を平滑化する積分回路と、該
積分回路の出力を各々異なるレベルの基準電圧と
比較する2つの電圧比較回路と、該2つの電圧比
較回路の出力の排他的論理和をとりその信号によ
つて前記時定数可変型積分回路のスイツチを制御
する排他的論理和回路とから成り、前記第2の時
定数と第3の時定数を前記第1の時定数よりも小
さくなし、入力信号のステツプ的変化時において
前記スイツチを切替えて前記時定数可変型積分回
路の時定数を前記第1の時定数から第2の時定数
に切替えることを特徴とするAGC回路である。(Structure of the Invention) The present invention includes a variable gain circuit that makes the input/output gain variable by external control, an absolute value circuit that converts the output of the variable gain circuit into an absolute value, and a switch that changes the first time constant and the second time constant. a variable time constant integrating circuit that can be switched to a time constant and smoothes the output of the absolute value circuit to control the variable gain circuit; and an integrating circuit that has a third time constant and smoothes the output of the absolute value circuit. , two voltage comparator circuits that compare the outputs of the integrator circuits with reference voltages of different levels, and an exclusive OR of the outputs of the two voltage comparator circuits, and the variable time constant integrator circuit and an exclusive OR circuit that controls a switch, the second time constant and the third time constant being smaller than the first time constant, and switching the switch when the input signal changes stepwise. The AGC circuit is characterized in that the time constant of the variable time constant integrating circuit is switched from the first time constant to the second time constant.
(第1の実施例)
第3図は本発明の実施例によるAGC回路であ
り、31は信号入力端子、32は可変利得回路、
33は整流回路、34は平滑回路、35,36は
電圧比較回路、37は排他的論理和回路、38は
時定数可変型平滑回路、39はAGC信号出力端
子である。第3図において、一点鎖線で囲んだ部
分は、第1図に示した従来例のAGC回路に新た
に加えた回路部分であり、抵抗R2とコンデンサ
C2から成る積分回路は第1図の平滑回路に相当
する。抵抗R2とコンデンサC2、抵抗R2とR
3の並列抵抗値RpとコンデンサC2、抵抗R1
とコンデンサC1から成る各CR積分回路の時定
数を各々τ2=C2R2,τ3=C2Rp,τ4=C1R
1とし、入力のステツプ的なレベル変化の時定数
をτ1とすれば、τ1≒τ3<τ4≪τ2のように設定され
ている。(First Embodiment) FIG. 3 shows an AGC circuit according to an embodiment of the present invention, in which 31 is a signal input terminal, 32 is a variable gain circuit,
33 is a rectifier circuit, 34 is a smoothing circuit, 35 and 36 are voltage comparison circuits, 37 is an exclusive OR circuit, 38 is a variable time constant smoothing circuit, and 39 is an AGC signal output terminal. In Fig. 3, the part surrounded by a dashed line is a circuit part newly added to the conventional AGC circuit shown in Fig. 1, and the integrating circuit consisting of resistor R2 and capacitor C2 is the smoothing circuit shown in Fig. 1. corresponds to Resistor R2 and capacitor C2, resistor R2 and R
3 parallel resistance value R p , capacitor C2, and resistor R1
The time constants of each CR integrator circuit consisting of the
1 and the time constant of the stepwise level change of the input is τ 1 , then it is set as τ 1 ≈τ 3 <τ 4 ≪τ 2 .
第4図は第3図に示した本発明の実施例による
AGC回路の各部における信号波形を示し、第4
図aは信号入力端子31における入力信号、第4
図bは平滑回路34の出力信号、第4図cは電圧
比較回路35の出力信号、第4図dは電圧比較回
路36の出力信号、第4図eは排他的論理和回路
37の出力信号、第4図fは時定数可変型平滑回
路38の出力信号、第4図gは出力端子39にお
ける出力信号の各信号波形である。 FIG. 4 is based on the embodiment of the invention shown in FIG.
The signal waveforms in each part of the AGC circuit are shown, and the fourth
Figure a shows the input signal at the signal input terminal 31, the fourth
4b shows the output signal of the smoothing circuit 34, FIG. 4c shows the output signal of the voltage comparison circuit 35, FIG. 4d shows the output signal of the voltage comparison circuit 36, and FIG. 4e shows the output signal of the exclusive OR circuit 37. , FIG. 4f shows the output signal of the time constant variable smoothing circuit 38, and FIG. 4g shows the signal waveforms of the output signal at the output terminal 39.
次に第3図、第4図を用いて本発明の動作を説
明する。入力信号を第4図aに示す信号とする。
入力信号は可変利得回路32、整流回路33を通
り、平滑回路34において、入力信号がステツプ
変化した第4図aの S1 のところで時定数τ4で放
電する為、平滑回路34の出力は第4図b S11
のように変化する。次に電圧比較回路36にて比
較電圧VLと比較され、第4図d S12 に示すハイ
レベルとなる。この時電圧比較回路35の出力は
ハイレベルにホールドしていることから、排他的
論理和回路37の出力は第4図e S13 に示すよ
うに電圧比較回路36の出力を反転したものとな
る。時定数可変型平滑回路38のスイツチSWは
排他的論理和回路37の出力がロウレベルの時に
オンされる。スイツチSWがオンされると、時定
数可変型平滑回路38の時定数はτ3=C2Rp(≪
C2R2)となり、これによつて時定数可変型平
滑回路38の出力はτ3の時定数で放電して第4図
fに示すような波形となり、その出力が可変利得
回路32を制御し、AGC信号出力端子39の出
力信号もτ3の時定数で利得制御される(第4図
g)。利得制御された結果、整流回路33の出力
は低下したレベルが復旧し、平滑回路34の出力
もレベルが上昇して再び比較電圧VLより高くな
り、電圧比較回路36の出力はロウレベルとな
る。続いて排他的論理和回路37の出力はハイレ
ベルとなり、時定数可変型平滑回路38のスイツ
チSWがオフするため、時定数可変型平滑回路3
8の時定数はτ2にもどる。 Next, the operation of the present invention will be explained using FIGS. 3 and 4. Let the input signal be the signal shown in FIG. 4a.
The input signal passes through the variable gain circuit 32 and the rectifier circuit 33, and is discharged in the smoothing circuit 34 with a time constant τ 4 at S1 in FIG. Figure b S11
It changes like this. Next, it is compared with the comparison voltage V L in the voltage comparison circuit 36, and becomes a high level as shown at d S12 in FIG. 4. At this time, since the output of the voltage comparison circuit 35 is held at a high level, the output of the exclusive OR circuit 37 becomes the inverted version of the output of the voltage comparison circuit 36, as shown in FIG. 4 e S13. The switch SW of the variable time constant smoothing circuit 38 is turned on when the output of the exclusive OR circuit 37 is at a low level. When the switch SW is turned on, the time constant of the variable time constant smoothing circuit 38 is τ 3 =C2R p (≪
C2R2), and as a result, the output of the variable time constant smoothing circuit 38 is discharged with a time constant of τ 3 and becomes a waveform as shown in FIG. The output signal of the signal output terminal 39 is also gain controlled with a time constant of τ 3 (FIG. 4g). As a result of the gain control, the output of the rectifier circuit 33 recovers from the lowered level, the level of the output of the smoothing circuit 34 also increases and becomes higher than the comparison voltage V L again, and the output of the voltage comparison circuit 36 becomes low level. Subsequently, the output of the exclusive OR circuit 37 becomes high level, and the switch SW of the variable time constant smoothing circuit 38 is turned off, so that the variable time constant smoothing circuit 3
The time constant of 8 returns to τ 2 .
次に入力信号の入力レベルがステツプ的に上昇
した時(第4図a S2 )、平滑回路34の出力が
電圧比較回路35において比較電圧VHより高く
なり(第4図b S21 )、電圧比較回路35の出
力はロウレベルとなる(第4図c S22 )。この
時、電圧比較回路36の出力はロウレベルである
から、排他的論理和回路37の出力はロウレベル
(第4図e S23 )となり、時定数可変型平滑回
路38のスイツチSWを切替えて時定数可変型平
滑回路38の時定数をτ2からτ3(τ2≫τ3)に切替
え、AGC出力信号はτ3(=C2Rp)の時定数で過
渡応答が復旧する。その後前述した場合と同様
に、平滑回路34の出力が比較電圧VHよりも低
くなる為電圧比較回路35の出力がハイレベル、
電圧比較回路36の出力がロウレベルとなる為、
排他的論理和回路37の出力がハイレベルとな
り、その結果時定数平滑回路38の時定数はスイ
ツチSWがオフされてτ3からτ2に切替る。従つて、
第3図に示したAGC回路では第4図aに示した
入力信号に対して第4図gに示したAGC出力を
得ることができる。 Next, when the input level of the input signal increases stepwise (Fig. 4a S2), the output of the smoothing circuit 34 becomes higher than the comparison voltage V H in the voltage comparator circuit 35 (Fig. 4b S21), and the voltage comparison The output of the circuit 35 becomes low level (c S22 in FIG. 4). At this time, since the output of the voltage comparator circuit 36 is at low level, the output of the exclusive OR circuit 37 is at low level (e S23 in FIG. 4), and the time constant is changed by switching the switch SW of the variable time constant type smoothing circuit 38. The time constant of the type smoothing circuit 38 is switched from τ 2 to τ 3 (τ 2 >>τ 3 ), and the transient response of the AGC output signal is restored with the time constant of τ 3 (=C2R p ). After that, as in the case described above, the output of the smoothing circuit 34 becomes lower than the comparison voltage VH , so the output of the voltage comparison circuit 35 becomes high level.
Since the output of the voltage comparison circuit 36 becomes low level,
The output of the exclusive OR circuit 37 becomes high level, and as a result, the time constant of the time constant smoothing circuit 38 is switched from τ 3 to τ 2 as the switch SW is turned off. Therefore,
The AGC circuit shown in FIG. 3 can obtain the AGC output shown in FIG. 4g for the input signal shown in FIG. 4a.
本実施例のAGC回路においては、入力レベル
のステツプ的な変化に対して出力の過渡応答時間
を大巾に短縮でき、エラー時間を短かくすること
ができる利点を有する。 The AGC circuit of this embodiment has the advantage that the transient response time of the output to a stepwise change in the input level can be greatly shortened, and the error time can be shortened.
(第2の実施例)
第1の実施例ではアナログ信号処理の場合につ
いて説明したが、これをデイジタル信号処理にお
き替えても同様の効果を得ることができる。すな
わち、第1の実施例にて説明した第3図におい
て、可変利得回路32を乗算回路に、整流回路3
3を絶対値回路に、平滑回路34をアキユームレ
ータ(積算回路)に、電圧比較回路35,36を
マグニチユードコンパレータに、時定数可変型平
滑回路38を入力利得可変型アキユームレータに
各々置き換えてデイジタル信号処理回路を構成す
ることによつても前記第1の実施例と同じ機能を
有するAGC回路を構成することができる。(Second Embodiment) Although the first embodiment describes the case of analog signal processing, similar effects can be obtained even if this is replaced with digital signal processing. That is, in FIG. 3 described in the first embodiment, the variable gain circuit 32 is used as a multiplier circuit, and the rectifier circuit 3 is used as a multiplier circuit.
3 as an absolute value circuit, smoothing circuit 34 as an accumulator (integration circuit), voltage comparison circuits 35 and 36 as a magnitude comparator, and variable time constant smoothing circuit 38 as a variable input gain accumulator. By replacing it with a digital signal processing circuit, it is also possible to construct an AGC circuit having the same function as that of the first embodiment.
この場合、第1の実施例と同じ効果を提供でき
るとともに、LSI化が可能となる利点を有するこ
とができる。 In this case, it is possible to provide the same effects as the first embodiment, and also to have the advantage that LSI implementation is possible.
(発明の効果)
本発明はAGC回路において入力レベルのステ
ツプ的な変化に対して出力の過渡応答時間を大巾
に短縮できるので、モデムの受信部に利用するこ
とができる。又レベルのステツプ的な変化の検出
に微分回路を使用せずに積分回路で構成している
為、雑音に対する誤動作余裕において利点があ
り、更にレベルのステツプ的な変化の検出を
AGC出力側で行なつているので、ステツプ変化
検出出力が広いレベル範囲で得られるという利点
がある。(Effects of the Invention) The present invention can greatly shorten the transient response time of the output in response to stepwise changes in the input level in the AGC circuit, and therefore can be used in the receiving section of a modem. In addition, since it is configured with an integrator circuit instead of a differentiating circuit to detect step-like changes in level, it has an advantage in terms of margin for malfunction due to noise.
Since this is done on the AGC output side, it has the advantage that the step change detection output can be obtained over a wide level range.
第1図は従来例におけるAGC回路図、第2図
は第1図に示すAGC回路の各部における信号波
形図、第3図は本発明の実施例によるAGC回路
図、第4図は第3図に示すAGC回路の各部にお
ける信号波形図である。
31……信号入力端子、32……可変利得回
路、33……整流回路、34……平滑回路、3
5,36……電圧比較回路、37……排他的論理
和回路、38……時定数可変型平滑回路、39…
…出力端子、R1,R2,R3……抵抗、C1,
C2……コンデンサ、SW……スイツチ。
Figure 1 is an AGC circuit diagram of a conventional example, Figure 2 is a signal waveform diagram at each part of the AGC circuit shown in Figure 1, Figure 3 is an AGC circuit diagram of an embodiment of the present invention, and Figure 4 is a diagram of the AGC circuit shown in Figure 3. FIG. 3 is a signal waveform diagram at each part of the AGC circuit shown in FIG. 31... Signal input terminal, 32... Variable gain circuit, 33... Rectifier circuit, 34... Smoothing circuit, 3
5, 36... Voltage comparison circuit, 37... Exclusive OR circuit, 38... Variable time constant smoothing circuit, 39...
...output terminal, R1, R2, R3...resistance, C1,
C2...Capacitor, SW...Switch.
Claims (1)
利得回路と、該可変利得回路の出力を絶対値化す
る絶対値回路と、スイツチ切替えにより第1の時
定数と第2の時定数に切替えでき前記絶対値回路
の出力を平滑化して前記可変利得回路を制御する
時定数可変型積分回路と、第3の時定数をもち前
記絶対値回路の出力を平滑化する積分回路と、該
積分回路の出力を各々異なるレベルの基準電圧と
比較する2つの電圧比較回路と、該2つの電圧比
較回路の出力の排他的論理和をとりその信号によ
つて前記時定数可変型積分回路のスイツチを制御
する排他的論理和回路とから成り、前記第2の時
定数と第3の時定数を前記第1の時定数よりも小
さくなし、入力信号のステツプ的変化時において
前記スイツチを切替えて前記時定数可変型積分回
路の時定数を前記第1の時定数から第2の時定数
に切替えることを特徴とするAGC回路。1. A variable gain circuit whose input/output gain is made variable by external control, an absolute value circuit which converts the output of the variable gain circuit into an absolute value, and the above-mentioned circuit which can be switched between a first time constant and a second time constant by switching a switch. a variable time constant type integrator circuit that smoothes the output of the absolute value circuit to control the variable gain circuit; an integrator circuit having a third time constant that smoothes the output of the absolute value circuit; and an output of the integrator circuit. two voltage comparator circuits that compare the voltages with reference voltages of different levels, and an exclusive OR circuit that performs an exclusive OR of the outputs of the two voltage comparator circuits and controls a switch of the variable time constant integrator circuit by that signal. The second time constant and the third time constant are made smaller than the first time constant, and the switch is switched when the input signal changes stepwise to produce the variable time constant type. An AGC circuit characterized in that the time constant of the integrating circuit is switched from the first time constant to the second time constant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP285883A JPS59128806A (en) | 1983-01-13 | 1983-01-13 | Agc circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP285883A JPS59128806A (en) | 1983-01-13 | 1983-01-13 | Agc circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59128806A JPS59128806A (en) | 1984-07-25 |
| JPH0124444B2 true JPH0124444B2 (en) | 1989-05-11 |
Family
ID=11541075
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP285883A Granted JPS59128806A (en) | 1983-01-13 | 1983-01-13 | Agc circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59128806A (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0496510A (en) * | 1990-08-13 | 1992-03-27 | Nec Corp | Automatic level control circuit |
| US5548833A (en) * | 1994-06-03 | 1996-08-20 | Transwitch Corporation | Data independent automatic gain control circuit for telecommunication applications |
| US5697074A (en) * | 1995-03-30 | 1997-12-09 | Nokia Mobile Phones Limited | Dual rate power control loop for a transmitter |
| AU5906400A (en) * | 1999-07-02 | 2001-01-22 | Nokia Networks Oy | Power control for non-constant envelope modulation |
| JP4299416B2 (en) | 1999-10-18 | 2009-07-22 | 株式会社ルネサステクノロジ | Peak detection type AGC circuit |
| FR2884659B1 (en) * | 2005-04-18 | 2007-07-13 | Siemens Vdo Automotive Sas | DEVICE FOR AUTOMATICALLY CONTROLLING THE GAIN OF A SIGNAL AMPLIFIER AND AMPLIFIER PROVIDED WITH SUCH A DEVICE |
| JP4898360B2 (en) * | 2005-11-16 | 2012-03-14 | 三星電子株式会社 | Automatic gain controller |
| JP5188365B2 (en) * | 2008-11-17 | 2013-04-24 | 三菱電機株式会社 | Signal transmission system |
| JP5280256B2 (en) * | 2009-03-12 | 2013-09-04 | 住友電工デバイス・イノベーション株式会社 | Electronic circuit |
| JP2015046725A (en) * | 2013-08-27 | 2015-03-12 | 株式会社五洋電子 | Tone squelch circuit |
| JP6539908B2 (en) * | 2015-01-08 | 2019-07-10 | 日本無線株式会社 | Power controller |
-
1983
- 1983-01-13 JP JP285883A patent/JPS59128806A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59128806A (en) | 1984-07-25 |
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