JPH01248260A - Input/output address converting system - Google Patents

Abstract

PURPOSE:To improve the transplantation property of a software and to execute an emulation of the software on other machine kind by separating a logical address from a physical address and allowing the software for executing an input/output access to be independent from a hardware. CONSTITUTION:At the time of an input/output access, in accordance with a logical address generated by a CPU 1, a physical input/output address is obtained by executing an access to a memory 6, and supplied to a selector 7. It is decoded by a decoder 11, and an input/output selecting signal is obtained. The selector 7 is controlled by decoding a cycle defining signal obtained from the CPU 1. In case when the input/output access is not executed, the address outputted from the CPU 1 becomes an address connected to a bus as it is. In such a way, the logical address and the physical address are separated, the input/output address which is looked at from the CPU 1 can be made variable, the transportation property of a software is raised, and the maintenance of compatibility with a conventional machine is attained easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an input/output address conversion method suitable for use in a personal computer.

(Prior Art) FIG. 2 shows an example of a connection configuration between a CPU and an input cube vice in a conventional computer system.

In the figure, 21 is a CPU, and 22 is an address decoder that converts an input/output address into an input/output selection signal.

Reference numeral 23 denotes an input/output device, 24 a line 25 through which an address (upper) output by the CPUI is propagated, a line through which a lower address is propagated, and has the number of bits necessary to define the input/output space. 26 is a line on which an input/output access definition signal indicating input/output access from the cPU 21 is propagated, 27 is an input/output selection signal obtained by decoding the signal propagated on lines 25 and 26, and 28 is a data bus It is.

(Problems to be Solved by the Invention) According to the above-mentioned conventional example, the input/output addresses seen from the software running on the CPU are fixed by the hardware. Therefore, the portability of the software was low, and there were problems in making it compatible with other models.

The present invention has been made based on the above circumstances.
It is an object of the present invention to provide an input/output address conversion method that can increase the portability of operating software and ensure compatibility with other models by allowing input/output addresses seen from the U.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention has a control circuit for input/output device access that converts a logical input/output address outputted by a CPU into a physical address. A memory that stores the physical input/output address corresponding to the address, and a CPU that stores either the address output by the CPU or the converted physical input/output address that is the memory output.
It is composed of a selector that selects and outputs a cycle definition signal outputted by U, and a decoder that generates an input/output selection signal from the physical input/output address that follows the CPU and selector output.

(Function) At the time of access, the memory is accessed according to the logical address generated by the CPU to obtain the physical input/output address, and the obtained physical input/output address is supplied to the selector. This is decoded by a decoder to obtain an input/output selection signal. Selector control is by CPU
This is done by decoding the cycle definition signal obtained from.

If it is not an input/output access, the address output from the CPU becomes the address directly connected to the bus.

As a result, logical addresses and physical addresses are separated, and the input/output addresses visible to the CPU can be made variable, increasing the portability of software and easily maintaining compatibility with conventional machines.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a CPU and J is an input/output device. 3 is a line on which the upper address generated by the CPUI is propagated, and 4 is a line on which the lower address is propagated, and these are combined to form a logical input/output address. 5 is a line through which physical input/output addresses are propagated. 6 is a RAM that converts logical input/output addresses into physical input/output addresses. 7
is a selector that selects either one of the signals propagating through lines 4 and 5. 8 is the output of the selector and the line on which the lower address connected to the bus is propagated, and 9 is the line on which the cycle definition signal indicating whether the access from 1 is hard, input/output, or memory or input/output is propagated. Line 10 is a line on which an input/output access definition signal indicating input/output access is propagated. A decoder 11 decodes a cycle definition signal, and a decoder 12 generates a selection signal from a physical input/output address. 13 is a line through which an input/output selection signal is propagated. 14 is a control circuit that generates a write signal for the RAM 6. 15 is a line through which a write signal is propagated, 16 is a data bus, and 17 is a buffer for connecting the data bus 16 and the RAM 6.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail. R
A physical input/output address is stored in AM6, and a logical input/output address is converted into a physical input/output address here. 2
The bit widths of the two addresses are the same, that is, the sizes of the logical input/output address space and the physical input/output address space are the same, and the contents of IA and RAM6 are transferred from the CPU to the data bus 16.
, are written into the RAM 6 through the buffer 17 under the control of the output signal (line 15) of the write signal generation circuit 14.

During input/output access, the lower address (logical input/output address; line 4) from the CPUJ and the read physical input/output address (line 5) are transferred to the lower address (line 8) connected to the bus through the selector 7. , this is decoded by the address decoder 12 to obtain an input/output selection signal (line 13). When it is not an input/output access, the lower address from cpil becomes the lower address connected to the bus through the entire selector 7. The selector 7 is controlled by an input/output access definition signal (line 10) obtained by decoding the cycle definition signal (line 9) from the CPUI by the decoder 1.

〔Effect of the invention〕

According to the present invention as described above, by separating logical addresses from physical addresses, software that performs input/output access can be made independent from hardware. This improves software portability and enables emulation of software on other models.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing an example of a conventional configuration. 1...CPU, j? ...I/O device, 6...
RAM. 7...Selector, 11.12...Decoder, 17.
··buffer. Figure 1 Figure 2

Claims (1)

[Claims] In a computer system in which a CPU and multiple input/output devices are connected, there is a memory that stores physical input/output addresses corresponding to logical input/output addresses output by the CPU, and a memory that stores physical input/output addresses corresponding to logical input/output addresses output by the CPU, and a memory that stores the addresses output by the CPU and the converted memory outputs. Either one of the physical input/output addresses
It is equipped with a selector that selects and outputs according to the cycle definition signal outputted by U, and a decoder that generates an input/output selection signal from the physical input/output address according to the CPU and selector output, and when accessing the input/output device, the memory is An input/output address conversion method characterized by converting a logical input/output address into a physical input/output address consisting of an equal number of bits through a CPU, thereby making the input/output address visible to a CPU variable.