JPH0125233B2 - - Google Patents
Info
- Publication number
- JPH0125233B2 JPH0125233B2 JP61185669A JP18566986A JPH0125233B2 JP H0125233 B2 JPH0125233 B2 JP H0125233B2 JP 61185669 A JP61185669 A JP 61185669A JP 18566986 A JP18566986 A JP 18566986A JP H0125233 B2 JPH0125233 B2 JP H0125233B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- diffusion
- isolation region
- anode
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/20—Breakdown diodes, e.g. avalanche diodes
- H10D8/25—Zener diodes
Landscapes
- Element Separation (AREA)
Description
【発明の詳細な説明】
(イ) 産業上の利用分野
本発明はモノリシツク集積回路に組込まれるダ
イオードの改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvements in diodes incorporated in monolithic integrated circuits.
(ロ) 従来の技術
従来のモノリシツク集積回路に組込まれるツエ
ナー特性を有するダイオードは第2図に示す如
く、P型の半導体基板1と基板1上に設けられた
N型エピタキシヤル層2とエピタキシヤル層2を
貫通し複数の島領域3,3を形成するP+型の分
離領域4とを備え、分離領域4をアノード領域5
と兼用しアノード領域5にN+型のカソード領域
6を設け各領域5,6にオーミツク接触したアノ
ード電極7およびカソード電極8より構成されて
いる。(b) Prior Art A diode with Zener characteristics that is incorporated into a conventional monolithic integrated circuit, as shown in FIG. A P + type isolation region 4 that penetrates the layer 2 and forms a plurality of island regions 3, 3, and the isolation region 4 is connected to an anode region 5.
An N + type cathode region 6 is provided in the anode region 5 and is composed of an anode electrode 7 and a cathode electrode 8 which are in ohmic contact with each region 5 and 6.
(ハ) 発明が解決しようとする問題点
しかしながら、斯る構造ではアノード領域5が
分離領域4で兼用されているので、アノード領域
5表面に高濃度不純物拡散時に発生する結晶欠陥
が多くなる。即ち、分離領域4はエピタキシヤル
層2を貫通させる様に拡散しているので、高濃度
不純物拡散を長時間行う必要があり、その表面に
極めて結晶欠陥が発生し易くなるからである。こ
の結果第4図に点線で示す様に結晶欠陥によるリ
ーク電流等が発生してツエナー特性が悪化する欠
点があつた。(c) Problems to be Solved by the Invention However, in such a structure, since the anode region 5 is also used as the separation region 4, many crystal defects occur on the surface of the anode region 5 when high concentration impurities are diffused. That is, since the isolation region 4 is diffused so as to penetrate the epitaxial layer 2, it is necessary to carry out high-concentration impurity diffusion for a long time, and crystal defects are extremely likely to occur on the surface thereof. As a result, as shown by the dotted line in FIG. 4, leakage current and the like occur due to crystal defects, resulting in deterioration of Zener characteristics.
(ニ) 問題点を解決するための手段
本発明は斯上した欠点に鑑みてなされ、高濃度
不純物拡散による分離領域14表面に重ねて低濃
度不純物拡散によるアノード領域15を形成する
ことにより、従来の欠点を除去したモノリシツク
集積回路に組込まれるダイオードの製造方法を実
現するものである。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks, and by forming an anode region 15 formed by diffusion of a low concentration impurity overlapping the surface of the isolation region 14 formed by diffusion of a high concentration impurity, it is possible to solve the problem by The purpose of this invention is to realize a method of manufacturing a diode incorporated in a monolithic integrated circuit which eliminates the drawbacks described above.
(ホ) 作用
本発明によれば、分離領域14表面に発生した
結晶欠陥はアノード領域15の低濃度不純物拡散
によつてアニールされて減少する。この結果特性
良好なツエナー特性が得られる。(e) Effect According to the present invention, crystal defects generated on the surface of the isolation region 14 are annealed and reduced by the diffusion of low concentration impurities in the anode region 15. As a result, good Zener characteristics can be obtained.
(ヘ) 実施例
以下第1図および第3図を参照して本発明の一
実施例を詳述する。(f) Embodiment An embodiment of the present invention will be described in detail below with reference to FIGS. 1 and 3.
本発明に依るダイオードは第1図に示す如く、
P型の半導体基板11と基板11上に設けられた
N型のエピタキシヤル層12とエピタキシヤル層
12を貫通し且つエピタキシヤル層12を複数の
島領域13,13に分離するP+型の分離領域1
4とを備え、分離領域14表面から低濃度不純物
拡散により形成されたP型のアノード領域15と
アノード領域15表面に拡散されたN+型のカソ
ード領域16と各領域15,16にオーミツク接
触したアノード電極17とカソード電極18より
構成されている。19は酸化膜である。 The diode according to the present invention is as shown in FIG.
A P type semiconductor substrate 11, an N type epitaxial layer 12 provided on the substrate 11, and a P + type separation that penetrates the epitaxial layer 12 and separates the epitaxial layer 12 into a plurality of island regions 13, 13. Area 1
4, and was in ohmic contact with each of the regions 15 and 16, with a P-type anode region 15 formed by low concentration impurity diffusion from the surface of the isolation region 14 and an N + type cathode region 16 diffused on the surface of the anode region 15. It is composed of an anode electrode 17 and a cathode electrode 18. 19 is an oxide film.
本発明の特徴は分離領域14表面に低濃度不純
物拡散によるアノード領域15を形成することに
ある。分離領域14はボロンBのデポジツト及び
ドライブインという一般的な熱拡散工程が利用さ
れ、まずはシート抵抗Rs=20Ω・cm-2とボロン
Bの固溶度限界付近の高濃度不純物デポジツトが
行なわれ(初期拡散)、続いて1200℃、10〜15時
間という長時間のドライブイン(引延ばし拡散)
によつて拡散深さ15〜20μmに形成する。この様
な高濃度不純物拡散を長時間行う為、分離領域1
4の表面には多くの結晶欠陥を発生している。ま
た、長時間の引延ばし拡散により前記初期拡散さ
れた不純物が拡散されるので、分離領域14表面
の不純物濃度はデポジツト時よりは相当低下し、
表面濃度が1019atoms・cm-3程度となるような拡
散領域となる。さらに、プレーナ技術においては
拡散と同時に酸化膜19の形成が不可避の技術で
あり、酸化膜19へのボロンBの拡散も不可避的
に行なわれるので、その結果分離領域14の最表
面の不純物濃度は1017〜1018atoms・cm-3に低下
(表面デプリート)する。 A feature of the present invention is that an anode region 15 is formed on the surface of the isolation region 14 by diffusing low concentration impurities. For the separation region 14, a general thermal diffusion process of boron B deposit and drive-in is used, and first, a high concentration impurity deposit with a sheet resistance Rs = 20 Ω cm -2 and near the solid solubility limit of boron B is performed ( initial diffusion), followed by a long drive-in (extension diffusion) at 1200°C for 10-15 hours.
The diffusion depth is 15 to 20 μm. In order to carry out such high-concentration impurity diffusion for a long time, the isolation region 1
Many crystal defects are generated on the surface of No. 4. In addition, since the initially diffused impurities are diffused by prolonged diffusion over a long period of time, the impurity concentration on the surface of the isolation region 14 is considerably lower than that at the time of deposition.
This becomes a diffusion region where the surface concentration is about 10 19 atoms·cm -3 . Furthermore, in the planar technology, the formation of the oxide film 19 at the same time as the diffusion is unavoidable, and the diffusion of boron B into the oxide film 19 is also unavoidable.As a result, the impurity concentration at the outermost surface of the isolation region 14 is reduced. It decreases to 10 17 to 10 18 atoms cm -3 (surface depletion).
斯様に形成された分離領域14に重ねて、アノ
ード領域15が再度ボロンBのデポジツト及びド
ライブインという一般的な拡散手法により形成さ
れる。即ち、アノード拡散は、まずシート抵抗
Rs=200Ω・cm-2と、分離拡散時よりは低い不純
物濃度でボロンBのデポジツト(初期拡散)が行
なわれ、続いて1200℃、3〜4時間の熱処理(引
延ばし拡散)により拡散深さ1〜2μmの拡散領
域を形成する。その際、分離領域14は引延ばし
拡散によつて表面濃度が固溶度以下に低下してい
るので、アノード領域15形成用不純物のデポジ
ツトが可能である。具体的には、NPNトランジ
スタのベース拡散等が利用でき、拡散後のアノー
ド領域15の表面濃度は5×1018atoms・cm-3程
度となる。結果、分離領域14とアノード領域1
5とが重畳した部分のボロンBの不純物濃度は、
両者のボロンBが加算されて5.1×1016〜6×
1018atoms・cm-3となる。その後、アノード領域
15表面に再度熱拡散により表面濃度
1020atoms・cm-3程度のカソード領域16を形成
して、第3図に示す如き濃度プロフアイルを有す
る本願のダイオードが製造される。 An anode region 15 is again formed overlying the isolation region 14 formed in this manner by a common diffusion method of depositing boron B and drive-in. That is, the anode diffusion first increases the sheet resistance.
Boron B is deposited (initial diffusion) at an impurity concentration of Rs = 200 Ω cm -2 , which is lower than that during separation diffusion, and then heat treatment (extension diffusion) at 1200°C for 3 to 4 hours increases the diffusion depth. Form a diffusion region of 1-2 μm. At this time, since the surface concentration of the separation region 14 is reduced to below the solid solubility due to stretching diffusion, it is possible to deposit impurities for forming the anode region 15. Specifically, base diffusion of an NPN transistor can be used, and the surface concentration of the anode region 15 after diffusion is about 5×10 18 atoms·cm −3 . As a result, separation region 14 and anode region 1
The impurity concentration of boron B in the overlapped part with 5 is:
Boron B of both is added and becomes 5.1×10 16 ~6×
10 18 atoms・cm -3 . After that, the surface concentration is again applied to the surface of the anode region 15 by thermal diffusion.
By forming a cathode region 16 of about 10 20 atoms·cm -3 , a diode of the present invention having a concentration profile as shown in FIG. 3 is manufactured.
この様に、アノード領域15とエピタキシヤル
層12に比べて浅く形成されるので、分離領域1
4よりは低濃度の不純物拡散で短時間で形成され
る。このためアノード領域15の形成工程ではエ
ピタキシヤル層12表面に新たな結晶欠陥が生じ
ることが無く、しかも分離領域14表面に発生し
ていた多くの結晶欠陥はアノード領域15の低濃
度不純物拡散時にアニールされて減少するのであ
る。従つてアノード領域15は分離領域14に重
ねて形成され重なつた部分の不純物濃度が分離領
域14よりも高くなるにも拘わらず、その表面の
結晶欠陥は分離領域14表面より大幅に減少す
る。この結果、第4図に実線で示す如く良好なツ
エナー特性が得られ、従来よりその特性を大幅に
改善できる。 In this way, since the anode region 15 and the epitaxial layer 12 are formed shallower than the anode region 15 and the epitaxial layer 12, the isolation region 1
4, it is formed in a shorter time by diffusion of impurities at a lower concentration. Therefore, no new crystal defects are generated on the surface of the epitaxial layer 12 in the process of forming the anode region 15, and many crystal defects that have occurred on the surface of the isolation region 14 are annealed during the diffusion of low concentration impurities in the anode region 15. Therefore, it decreases. Therefore, although the anode region 15 is formed overlapping the isolation region 14 and the impurity concentration in the overlapping portion is higher than that of the isolation region 14, the crystal defects on its surface are significantly reduced compared to the surface of the isolation region 14. As a result, good Zener characteristics can be obtained as shown by the solid line in FIG. 4, and the characteristics can be significantly improved compared to the conventional one.
また、本願のダイオードが特性向上する他の理
由として、(1)分離領域14の表面デプリートをア
ノード領域15の濃度プロフアイルが補償するこ
と、(2)結晶欠陥を有する分離領域14表面のシリ
コン結晶がアノード領域15形成時の酸化膜19
生成の為に消費されること、があげられる。 Further, other reasons why the characteristics of the diode of the present application are improved include (1) the concentration profile of the anode region 15 compensates for surface depletion of the isolation region 14, and (2) silicon crystal on the surface of the isolation region 14 having crystal defects. is the oxide film 19 when forming the anode region 15
One example is that it is consumed for the purpose of production.
(ト) 発明の効果
以上に説明した如く、本発明に依れば分離領域
14表面に重ねてアノード領域15を形成し、該
アノード拡散により分離領域14の結晶欠陥をア
ニールして除去するので、第4図に示す如く表面
リークの少い、良好なツエナー特性を有するダイ
オードを得ることができる。また本発明は分離領
域内に良好なツエナーダイオードを得ることによ
りモノリシツク集積回路の集積度向上に寄与でき
る有益なものである。(g) Effects of the Invention As explained above, according to the present invention, the anode region 15 is formed overlapping the surface of the isolation region 14, and crystal defects in the isolation region 14 are annealed and removed by the anode diffusion. As shown in FIG. 4, a diode having good Zener characteristics with little surface leakage can be obtained. Furthermore, the present invention is advantageous in that it can contribute to improving the degree of integration of monolithic integrated circuits by obtaining a good Zener diode in the isolation region.
第1図は本発明のダイオードを説明する断面
図、第2図は従来のダイオードを説明する断面
図、第3図は本発明ダイオードの濃度プロフアイ
ルを示す特性図、第4図は従来と本発明のツエナ
ー特性を示す特性図である。
11は半導体基板、12はエピタキシヤル層、
13は島領域、14は分離領域、15はアノード
領域、16はカソード領域、17はアノード電
極、18はカソード電極である。
FIG. 1 is a cross-sectional view of the diode of the present invention, FIG. 2 is a cross-sectional view of a conventional diode, FIG. 3 is a characteristic diagram showing the concentration profile of the diode of the present invention, and FIG. 4 is a cross-sectional view of the diode of the present invention. FIG. 3 is a characteristic diagram showing the Zener characteristics of the invention. 11 is a semiconductor substrate, 12 is an epitaxial layer,
13 is an island region, 14 is a separation region, 15 is an anode region, 16 is a cathode region, 17 is an anode electrode, and 18 is a cathode electrode.
Claims (1)
た逆導電型のエピタキシヤル層と該エピタキシヤ
ル層を貫通して複数の島領域を形成する一導電型
で高濃度不純物拡散による分離領域とを備えたモ
ノリシツク集積回路に於いて、前記分離領域に重
ねて一導電型で低濃度不純物拡散によるアノード
領域を設け、前記低濃度不純物拡散時のアニール
により前記分離領域の結晶欠陥を除去し、前記ア
ノード領域内に逆導電型のカソード領域を形成す
ることを特徴とするモノリシツク集積回路に組込
まれるダイオードの製造方法。1 A semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type provided on the substrate, and an isolation region of one conductivity type formed by high concentration impurity diffusion penetrating the epitaxial layer to form a plurality of island regions. In a monolithic integrated circuit comprising: an anode region of one conductivity type and diffused with a low concentration impurity so as to overlap the isolation region; crystal defects in the isolation region are removed by annealing during the diffusion of the low concentration impurity; A method of manufacturing a diode incorporated into a monolithic integrated circuit, characterized in that a cathode region of opposite conductivity type is formed within an anode region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61185669A JPS62115784A (en) | 1986-08-07 | 1986-08-07 | Diodes integrated into monolithic integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61185669A JPS62115784A (en) | 1986-08-07 | 1986-08-07 | Diodes integrated into monolithic integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62115784A JPS62115784A (en) | 1987-05-27 |
| JPH0125233B2 true JPH0125233B2 (en) | 1989-05-16 |
Family
ID=16174800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61185669A Granted JPS62115784A (en) | 1986-08-07 | 1986-08-07 | Diodes integrated into monolithic integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62115784A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2533855B2 (en) * | 1986-06-11 | 1996-09-11 | 沖電気工業株式会社 | Semiconductor integrated circuit device |
-
1986
- 1986-08-07 JP JP61185669A patent/JPS62115784A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62115784A (en) | 1987-05-27 |
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