JPH0577294B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an improvement in a method of manufacturing a semiconductor integrated circuit incorporating a vertical PNP transistor and a normal bipolar NPN transistor.

(b) Prior Art A conventional method for manufacturing a semiconductor integrated circuit will be explained using FIGS. 2A to 2E.

First, as shown in FIG. 2A, a P-type silicon substrate is used as the semiconductor substrate 1, and antimony (Sb) is selectively deposited on the substrate 1 to form a plurality of buried layers 2. Boron (B) is deposited on the surface of the substrate 1 surrounding the substrate 2 and on a predetermined buried layer 2 to form a lower diffusion layer 4 of the upper and lower isolation regions 3 and a collector buried layer 5 of the vertical PNP transistor.

Next, as shown in FIG. 2B, an N-type epitaxial layer 6 is formed to a predetermined thickness over the entire surface of the substrate 1 by a well-known vapor phase growth method.

Next, as shown in FIG. 2C, an epitaxial layer 6 is formed.
Phosphorus (P) is applied to the region corresponding to the collector buried layer 5 on the surface.
The base region 7 of the vertical PNP transistor is deposited by ion implantation. This ion implantation has a dose of
10 ¹² to 10 ¹³ cm ^-2 and an accelerating voltage of 80 to 100 KeV.

Next, as shown in FIG. 2D, an epitaxial layer 6 is formed.
Vertical type with upper diffusion layer 8 of upper and lower separation regions 3 from the surface
The collector lead-out area 9 of the PNP transistor is approximately
Selective diffusion is performed at 1200° C. for 3 to 4 hours, and at the same time, the buried layer 2, lower diffusion layer 4, collector buried layer 5, and base region 7 are driven in. In this process, the upper diffusion layer 8
The lower diffusion layer 4 continues to form the upper and lower isolation regions 3, and the epitaxial layer 6 is junction-separated to form first and second island regions 10 and 11. In addition, the collector lead-out region 9 reaches as far as the collector buried layer 5,
surrounding the base region 7; Specifically, if the thickness of the epitaxial layer 6 is 13 μm, the thickness of the upper diffusion layer 8 is approximately 9 μm.
m, the lower diffusion layer 4 and the collector buried layer 5 are formed to a depth of approximately 7 μm, and the base region 7 is formed to a depth of approximately 4 μm.

Next, as shown in FIG. 2E, an epitaxial layer 6 is formed.
Selectively diffuse boron (B) from the surface to form the first island region 1
0 is the emitter region 1 of the vertical PNP transistor.
2, a base region 13 of a normal NPN transistor is formed in the second island region 11, and then phosphorus (P) is selectively diffused to form a vertical type transistor in the first island region 10.
Base contact area 14 of PNP transistor
The second island region 11 has an emitter region 15 and a collector contact region 1 of the NPN transistor.
6 respectively.

The vertical type formed in the first island region 10 in this way
Since a part of the active base of the PNP transistor is formed by the base region 7 formed by ion implantation, the impurity concentration gradient causes an internal drift electric field to increase the traveling speed of carriers, resulting in a high gain bandwidth product f _T is obtained. Also vertical PNP
Since the h _FE of the transistor is almost determined by the base region 7, even if the resistivity and thickness of the epitaxial layer 6 vary, the h _FE does not vary much. A vertical PNP transistor with such a structure is known, for example, as described in Japanese Patent Application Laid-open No.
It is described in Publication No. 59-211270.

A normal bipolar NPN transistor is then formed in the second island region 11, and its base region 13 is connected to the emitter region 12 of the vertical PNP transistor and the emitter region 15 of the NPN transistor.
is formed by diffusion at the same time as the base contact region 14 of the vertical PNP transistor.

(c) Problems to be solved by the invention However, in the conventional manufacturing method, the vertical PNP is
Transistor base region 7 and collector buried layer 5
It's a drive-in. Therefore, even if the epitaxial layer 6 is made thinner in order to further increase the speed of both NPN transistors and vertical PNP transistors, vertical
In order to set f _T and V _CE (sat) of the PNP transistor to predetermined values, the upper diffusion layer 8 is formed by making the low concentration base region 7 sufficiently deep and using antimony (Sb).
Processing time is required to sufficiently peel up the collector buried layer 5 formed due to the difference in diffusion coefficients of boron (B) and boron (B). Moreover, in the upper diffusion layer 8 and the lower diffusion layer 4,
A state in which more impurities are supplied to the upper diffusion layer 8,
In other words, since the diffusion source film containing a large amount of boron (B) remains attached, it is inevitable that the upper diffusion layer 8
is formed deeper than the lower diffusion layer 4.

Therefore, even if the epitaxial layer 6 is made thinner, the upper diffusion layer 8 has to be formed quite deep, which has the disadvantage that lateral diffusion is large and the degree of integration cannot be improved.

(d) Means for Solving the Problems The present invention was made in view of the above-mentioned drawbacks, and the lower diffusion layer 4 and the collector buried layer 5 of the upper and lower separation regions 3 are made to have a thickness that is half the thickness of the epitaxial layer 6. At the same time, the base region 7 is formed to reach or almost reach the collector buried layer 5, and then the upper diffusion layer 8 and the collector lead-out region 9 of the upper and lower separation regions 3 are respectively lowered and diffused. By expanding the acid to reach layer 4 and collector buried layer 5,
The present invention provides a method for manufacturing a semiconductor integrated circuit in which bipolar NPN transistors and vertical PNP transistors coexist, with a greatly improved degree of integration.

(E) Effect According to the present invention, the upper diffusion layer 8 is formed after driving in the lower diffusion layer 4, the collector buried layer 5, and the base region 7 sufficiently deeply in advance, so that the upper diffusion layer 8 can be made shallow. , its lateral diffusion can be suppressed. Therefore, the degree of integration can be greatly improved without deteriorating the characteristics of the vertical PNP transistor.

(f) Example Hereinafter, the method for manufacturing a semiconductor integrated circuit of the present invention will be explained in detail with reference to FIGS. 1A to 1F.

First, as shown in FIG. 1A, a P-type silicon substrate is used as a semiconductor substrate 1, and antimony (Sb) is selectively deposited on the substrate 1 to form a plurality of buried layers 2. Boron (B) is deposited on the surface of the substrate 1 surrounding the substrate 2 and on a predetermined buried layer 2 to form a lower diffusion layer 4 of the upper and lower isolation regions 3 and a collector buried layer 5 of the vertical PNP transistor.

Next, as shown in FIG.
Form to a thickness of 7 μm.

Next, as shown in FIG.
Phosphorus (P) is applied to the region corresponding to the collector buried layer 5 on the surface.
The base region 7 of the vertical PNP transistor is deposited by ion implantation. This ion implantation has a dose of
10 ¹² to 10 ¹³ cm ^-2 and an accelerating voltage of 80 to 100 KeV.

Next, as shown in FIG.
By applying heat treatment at ℃ for 2 hours, the lower diffusion layer 4 of the upper and lower separation regions 3 and the collector buried layer 5 of the vertical PNP transistor are expanded and diffused by more than half the thickness of the epitaxial layer 6, and at the same time, the vertical type PNP
Drive in the base region 7 of the transistor. Specifically, the lower diffusion layer 4 and the collector buried layer 5
is spread by about 5μm, and the base region 7 is about 5μm.
Form to a depth of 3 μm. Therefore, the base region 7 completely reaches the collector buried layer 5. There is no problem even if the impurity concentration in the base region 7 is made slightly lower so that it does not completely reach the collector buried layer 5.

Next, as shown in FIG.
Vertical type with upper diffusion layer 8 of upper and lower separation regions 3 from the surface
The collector lead-out region 9 of the PNP transistor is selectively diffused at the same time, and the upper and lower isolation regions 3 are connected at a position shallower than half the thickness of the epitaxial layer 6.
Second island regions 10 and 11 are formed.

This step is a characteristic step of the present invention, in which the collector buried layer 5 and the lower diffusion layer 4 are raised and diffused in advance to a depth of more than half the thickness of the epitaxial layer 6.
At the same time, since the upper diffusion layer 8 and the collector lead-out region 99 are formed after the base region 7 is sufficiently deeply diffused, the upper diffusion layer 8 and the collector lead-out region 9 can be made as shallow as approximately 3 μm without being limited by the base region 7. , the diffusion time can be shortened to about 1 hour. Therefore, the lateral diffusion of the upper diffusion layer 8 and the collector lead-out region 9 is approximately
It can be suppressed to 3 μm, and the surface area occupied by them can be significantly reduced. Specifically, if the width of the diffusion window is 4 μm, the width of the upper diffusion layer 8 and the collector lead-out region 9 is approximately 10 μm. Note that the lower diffusion layer 4 is wider because it is formed deeper than the upper diffusion layer 8.
It is formed to have a thickness of approximately 14 μm.

Next, as shown in FIG.
Selectively diffuse boron (B) from the surface to form the first island region 1
0 is the emitter region 1 of the vertical PNP transistor.
2, a base region 13 of a normal NPN transistor is formed to a depth of approximately 2 μm in the second island region 11, and then phosphorus (P) is selectively diffused to form a vertical base region in the first island region 10. The base contact region 14 of a type PNP transistor is
The emitter region 15 and collector contact region 16 of the transistor are each formed to a depth of about 1.5 μm. Emitter region 1 of vertical PNP transistor
2 is formed on the surface of the base region 7 having a higher impurity concentration than the epitaxial layer 6, so it is formed somewhat shallower than the base region 13 of the NPN transistor.

In the semiconductor integrated circuit formed in this way, since the upper diffusion layer 8 can be made shallow, its lateral diffusion can be suppressed and the surface area occupied can be significantly reduced. At this time, although the lower diffusion layer 4 is formed to be wider than the upper diffusion layer 8, its peripheral edge is curved due to lateral diffusion and gradually becomes narrower upward from the surface of the substrate 1. Even if the width is about 14 μm at the surface, it becomes about 4 μm at the top of the lower diffusion layer 4, which is the line width of the diffusion window.
Therefore, the lower diffusion layer 4 formed wide cannot prevent an increase in the degree of integration on the surface of the epitaxial layer 6, and since the surface area occupied by the upper and lower separation regions 3 can be determined only by the upper diffusion layer 8, the degree of integration can be greatly improved. .

Further, a vertical PNP formed in the first island region 10
In the transistor, since the collector buried layer 5 and base region 7 are driven in at the same time as the lower diffusion layer 4, they can be formed sufficiently deep, and necessary and sufficient characteristics can be obtained with respect to variations in V _CE (sat), f _T , and h _FE . It will be done. In addition, since the collector lead-out region 9 is formed at the same time as the upper diffusion layer 8, the surface area occupied is greatly reduced, and the vertical PNP
It contributes to improving the degree of integration by reducing the pattern size of transistors.

The second island region 11 includes a base region 13 formed simultaneously with the emitter region 12 of the vertical PNP transistor, and an emitter region 15 and a collector contact region 16 formed simultaneously with the base contact region 14 of the vertical PNP transistor. The composing bipolar NPN transistor is a vertical PNP
It is integrated and coexists with the transistor.

(g) Effects of the Invention As explained above, according to the present invention, the upper diffusion layer 8 is formed after the lower diffusion layer 4 is raised by more than half the thickness of the epitaxial layer 6 and then diffused. It has the advantage that it can be made shallower, its lateral diffusion can be suppressed, and the degree of integration can be greatly improved. Furthermore, according to the present invention, the collector buried layer 5
Since the base region 7 and the base region 7 are driven in at the same time as the lower diffusion layer 4, the epitaxial layer 6 can be formed sufficiently deep even if it is made thin, and there is an advantage that a vertical PNP transistor and a bipolar transistor with good characteristics can coexist in an integrated manner. have

Further, according to the present invention, since the diffusion time of the upper diffusion layer 8 is short, there are fewer crystal defects on the surface of the epitaxial layer 6 due to thermal diffusion.
Since it is formed wider, it has the advantage that complete junction separation can be obtained even if there is some mask displacement.

[Brief explanation of the drawing]

1A to 1H are cross-sectional views for explaining the manufacturing method according to the present invention, and FIGS. 2A to 2E are cross-sectional views for explaining the conventional manufacturing method. 1 is a semiconductor substrate, 2 is a buried layer, 4 is a diffusion layer below the upper and lower isolation regions 3, 5 is a collector buried layer, 6 is an epitaxial layer, 7 is a base region of a vertical PNP transistor, 8 is a upper and lower isolation region This is the upper diffusion layer of 3.

Claims (1)

[Claims] 1. Impurities of opposite conductivity type forming a plurality of buried layers are attached to the surface of a semiconductor substrate of one conductivity type, and upper and lower separation regions are formed on the surface of the substrate surrounding the buried layers, and a lower diffusion layer is formed on the surface of the substrate surrounding the buried layers. a step of depositing an impurity of one conductivity type on the predetermined buried layers to form a collector buried layer of a vertical PNP transistor, and forming an epitaxial layer of the opposite conductivity type on the entire surface of the substrate by an epitaxial growth method. and re-diffusing each impurity adhering to the substrate surface upward during the epitaxial growth process, and adding relatively low impurity to a region corresponding to the collector buried layer on the surface of the epitaxial layer. a step of ion-implanting impurities of opposite conductivity type to form a base region of the vertical PNP transistor with a high concentration; stretching and diffusing the impurity forming the base region of the vertical PNP transistor until reaching a position above half the thickness of the layer and at the same time reaching a position below the top of the lower diffusion layer; An upper diffusion layer of the upper and lower isolation regions and a collector lead-out region of the vertical PNP transistor are formed from the surface of the epitaxial layer, and the upper and lower isolation regions are connected at a position deeper than the base of the NPN transistor. forming an island region and a second island region, selectively diffusing impurities of one conductivity type from the surface of the epitaxial layer, and forming an emitter region of the vertical PNP transistor on the surface of the base region of the first island region; A base region of an NPN transistor is formed in the second island region, and then an impurity of the opposite conductivity type is selectively diffused to form a base contact region of the vertical PNP transistor in the first island region. . A method of manufacturing a semiconductor integrated circuit, comprising the steps of forming emitter regions of the NPN transistors in the second island regions.