JPH0125445B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital filter applied to speech synthesis and the like.

Various speech synthesis methods have already been proposed, such as PACOR as a parameter synthesis method.
(partial auto correlation) method and LSP (line spectrum) method, which requires less information.
(line spectrum pair) method is known.
In such a system, a pulse generator that simulates vocal fold vibration of voiced sounds, a random noise generator that simulates turbulence noise of unvoiced sounds, a digital filter that changes filter coefficients according to parameters, and a DA It is equipped with a converter, performs voice synthesis through digital processing, and converts it into an analog voice signal using a DA converter.

The digital filter described above is composed of multipliers, adders, subtracters, delay elements, etc., and data and coefficients are input in series and calculations are performed by pipeline processing to simulate the vocal tract. . In such conventional digital filters, guard bits or the like are added between a plurality of parameters as word boundaries. Another disadvantage is that when the calculation result overflows, it affects subsequent calculations and deteriorates the synthesized speech.

The present invention enables a digital filter that performs digital arithmetic processing in a pipeline system to accurately perform arithmetic processing even on continuous data that omit guard bits etc. that are unnecessary for the original arithmetic operation.
Further, the purpose is to eliminate the influence when the calculation result overflows. Examples will be described in detail below.

FIG. 1 is a block diagram of an embodiment of the present invention, where MPL is a multiplier, D is a delay element, + is an adder,
- is the subtractor, a ₁ ~ a _o , b ₁ ~ b _o are the coefficients (multipliers) of the multiplier MPL (LSP parameters), x ₁ ~ x _o , y ₁ ~ y _o are the data (multiplicand) of the multiplier MPL , S ₁ to S _o are partial sums, and A is an amplitude coefficient. In this digital filter, the multiplier MPL, adder, and subtractor can be used in time division, so the input U
(t) and the output W(t) can be realized by the configuration shown in FIG.

In Figure 2, G1 to G6 are AND gates,
G7 to G9 are OR gates, DR1 to DR3 are delay registers, REG is a partial sum register, ZR is a register, DCNT is a control circuit that detects overflow and inserts "0", MPL is a multiplier, + is an adder, - is a The subtracter, F is the coefficient, and SYN is the output synchronization signal. When the control circuit DCNT detects an overflow, it sends out "0" and the AND gates G1~
By closing G6, "0" is inserted for a period corresponding to the number of parameters. Also multiplier
The coefficients a ₁ to a _o , b ₁ to b _o , and A of the MPL are inputted sequentially in a time-sharing manner, and the timing with the input U(t) is adjusted by the register ZR. Also output W
(t) is output from the AND gate G6 in synchronization with the output synchronization signal SYN.

The multiplier MPL has a configuration corresponding to the number of bits of the coefficient F, and consists of a first stage module, a basic module of (n-4) stages when the number of bits is n, a truncated upper module, and a final stage module. It is configured. Figure 3 is the first stage module, Figure 4 is the basic module, Figure 5 is the truncated upper module,
FIG. 6 shows the configuration of the final stage module. In each figure, D _A , D _B , and D _C are delay elements controlled by clocks with the same period, such as flip-flops, G10 to G14 are AND gates, G15 is a NAND gate, G16 is an inverter, G17, G18 is Noah Gate, ADD1
~ADD4 is an adder, *1 is a 1-bit delay polarity insertion circuit, SW is a switch, and SEL is a selection circuit.

1-bit delay polarity insertion circuit In this case, the connection is switched by a switch SW. Further, in the case of the same bit, that is, in the case of "0", "0" or "1", "1", the delay element D _C is switched and connected by the switch SW.

The output data of the OR gate G7 in FIG. 2 and the coefficient F are input to the first stage module shown in FIG. 3 at the same timing from the LSB (least significant bit), and the data is passed through four delay elements _D hand,
Further, the coefficients are inputted as data and coefficients to the next-stage basic module, respectively, through one delay element _DA , and the output of the adder ADD1 is inputted to the next-stage basic module as a partial sum of products. adder
In ADD1, the output of the AND gate G10 is input to the B terminal via the delay element D _C or the 1-bit delay polarity insertion circuit*1, the output of the AND gate G11 is input to the A terminal, and the carry from the _C0 terminal is input. It is input to the C _i terminal via the delay element _DA , and the partial sum is output from the Σ terminal.

The basic module shown in FIG. 4 is cascade-connected in (n-4) stages for the number of bits n of coefficients, as described above, and the output of the AND gate G10 of the first-stage module is a part of the product of the previous-stage module. The structure corresponds to the Japanese style.

The truncating/truncating upper module shown in Fig. 5 performs 0/1 rounding of binary numbers, and the last data, coefficients, and partial sums of products of the cascaded stage of the basic module are input, and the selection circuit SEL performs addition. The output of the C ₀ terminal or the output of the partial sum of _the product from the previous stage via the delay element D _B is selected and input to the C _i terminal of the device ADD3. is selected by the selection circuit SEL via the delay element DA, and is input to the C _i terminal via the delay element D _A to perform LSB rounding.

In the final stage module shown in FIG. 6, the timing signal T _Z becomes "0" corresponding to the number of effective bits, and at that timing, the AND signal is output regardless of whether the output of the NAND gate G15 is "1" or "0". Gate G
The output of 14 becomes "0". Also Noah Gate G17
The output of is also "0", the inputs of the C _i terminal and the A terminal of the adder ADD4 are "0", and the partial sum of the product from the previous stage is input to the B terminal, and is output from the Σ terminal, and the product output data becomes the LSB of

Figures 7 and 8 show the configurations of adders and subtracters, where G20, G21, G30, and G31 are exclusive OR gates;
34 is an AND gate, G25 and G35 are OR gates, G36 is an inverter, FF1 to FF4 are flip-flops, CLK is a clock, and WB is a signal that becomes "0" with a cycle of one parameter, and is a clear terminal of flip-flops FF2 and FF4. Applied to CLR and preset terminal PST.

The adder outputs the full addition output of inputs A and B from flip-flop FF1, and the carrier C=AB+BC+CA is output from flip-flop FF2, which is added to AND gates G22 to G24 and exclusive OR gate G21. Since the output of FF1 is applied to the data terminal D of the flip-flop FF1, a full addition output is obtained from the output terminal Q in accordance with the clock CLK applied to the clock terminal CK.

The subtracter performs full subtraction of A-B of inputs A and B, and input B is inverted by inverter G36.
The following operates similarly to an adder, with the MSB of one word
In the calculation, flip-flops FF2, FF4
is cleared, and carries or borrows are ignored.

FIG. 9 is a time chart for explaining the operation of the adder and subtracter. The signal WB becomes "0" in a period corresponding to one parameter, and the flip-flops FF2 and FF4 are reset and preset before the calculation cycle of the LSB of the data. is performed, and at that timing it becomes the MSB of the output. Note that A and B are the inputs of the adder or subtracter, and CLK is the clock.

The digital filter shown in FIG. 2 is constructed by combining the multipliers, adders, and subtracters described above with delay elements, etc., and further providing a control circuit DCNT for overflow detection and "0" insertion at the final stage of the loop. Ru. By performing calculation processing in a time-division manner, it is possible to perform a function similar to that of the digital filter shown in FIG.

For example, the specific operation of this control circuit DCNT is as follows:
If the MSB (polarity bit) of the value obtained by adding the filter internal calculation result and the input U(t) is different from the next bit (10... or 01...), it is considered an overflow and the route shown in Figure 2 is used. Gate is applied and the period of one filter operation cycle is “0”.
Perform [filling].

Next, an example of the operation of the multiplier will be described in the case where both data and coefficients are 6 bits.

Since the number of bits of the coefficient n is 6, the multiplier is
It consists of a first-stage module, two basic modules, a truncated module, and a final-stage module. Adopts two's complement display, data is “0.01011”
(+0.34375) and the coefficient is "11.1001" (-0.4375), the calculation shown in FIG. 10 will be performed. In the figure, the x marks indicate bits of other data that are input in series, and D ₀ , b ₁ , and Σ ₁ are the partial sums of the B terminal input, A terminal input, and product of the adder ADD1 of the first stage module. , D ₁ , b ₂ , Σ ₂ and D ₂ , b ₃ , Σ ₃
are the B terminal input, A terminal input, and the partial sum of the products of the adder ADD2 in the first and second stage of the basic module, respectively, and D ₃ , b ₄ , Σ ₄ are the B of the adder ADD3 of the truncated upper module. The terminal input, the A terminal input, and the partial sum of the product, D ₄ , b ₅ , C _i , Σ represent the B terminal input, A terminal input, C _i terminal input, and product output of the adder ADD4 of the final stage module.

In the round down module, the LSB of D ₃ (0)
is the symmetric bit for rounding. Also, in the final stage module, without performing the sign extension of D ₄ , leave the LSB ignored in other modules,
Set the bit of b ₅ corresponding to this LSB to “0” and set b ₅
ignore MSB. Also, the bit position that should be the LSB of _b5 , that is, the upper bit position of the above-mentioned "0" bit, is set as C _i = "1". Therefore, the product output Σ becomes "1.11011".

Figure 11 shows the case where the data is “0.11100” (+0.875) and the coefficient is “00.0111” (+0.4375). Since the absolute value of the data is 0.5 or more, the sine extension method (as indicated by the arrow) ), the product output Σ becomes "0.00100" and an accurate product output cannot be obtained, so the polarity insertion method (indicated by the arrow) is applied as shown in FIG. That is, a 1-bit delay polarity insertion circuit *1 is used. Therefore, the product output Σ is "0.01100".

As described above, the present invention does not insert surplus bits as word boundaries for each predetermined data length, and only requires computation of the effective bit length, thereby improving the computation speed. Further, in the multiplier, since the truncation upper module is provided before the final stage module, errors are reduced by rounding the final calculation result. Furthermore, since "0" is inserted for a period corresponding to the number of parameters by overflow detection, there is an advantage that the influence of overflow does not spread.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the principle of an embodiment of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention,
3, 4, 5, and 6 are block diagrams of the first-stage module, basic module, truncated upper module, and final-stage module that constitute the multiplier of the embodiment of the present invention, and FIG. and FIG. 8 is a block diagram of an adder and a subtracter according to an embodiment of the present invention, and FIG.
The figure is a time chart for explaining the operation of the adder and the subtracter, and FIGS. 10, 11, and 12 are diagrams for explaining the operation of the multiplier. MPL is a multiplier, + is an adder, - is a subtracter, D,
D _A , D _B , D _C are delay elements, DCNT is a control circuit that performs overflow detection and “0” insertion, ZR,
REG is a register, DR1 to DR3 are delay registers,
G1-G6, G10-G14, G22-G24,
G32-G34 are AND gates, G7-G9, G
35 is an OR gate, ADD1 to ADD4 are adders,
*1 is a 1-bit delay polarity insertion circuit, G15 is a NAND gate, and G17 and G18 are NOR gates.

Claims (1)

[Claims] 1. In a digital filter that is composed of multipliers, adders, subtracters, delay elements, registers, etc. and performs digital arithmetic processing in a pipeline method,
The multiplier has a cascade-connected configuration of an initial stage module, a basic module, a truncated upper module, and a final stage module, so that it is possible to input only the effective data length of multiple coefficients in series and perform calculations, and the final stage of the calculation loop of the filter At the step, an overflow of the operation result is detected, and when an overflow is detected, "0" is inserted into the register inside the filter for a period corresponding to the number of parameters that become the coefficient (multiplicand) or data (multiplicand) of the multiplier. A digital filter characterized by having a control circuit connected thereto. 2. In a digital filter that is composed of multipliers, adders, subtracters, delay elements, registers, etc. and performs digital arithmetic processing in a pipeline method,
The multiplier has a cascade-connected configuration of a first-stage module, a basic module, a truncated upper module, and a final-stage module, so that only the effective data length of a plurality of coefficients can be continuously input in series and operated. is the least significant bit of the data.
It has a configuration in which it is reset and preset before the LSB calculation cycle and performs calculations by continuously inputting only the valid data length in series, and at the final stage of the filter calculation loop, it detects overflows in the calculation results and also prevents overflows. A digital filter characterized in that a control circuit is connected to a register inside the filter to insert "0" at a period corresponding to the number of parameters serving as a coefficient (multiplier) or data (multiplicand) of the multiplier when detected.