JPH01256132A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01256132A
JPH01256132A JP63084351A JP8435188A JPH01256132A JP H01256132 A JPH01256132 A JP H01256132A JP 63084351 A JP63084351 A JP 63084351A JP 8435188 A JP8435188 A JP 8435188A JP H01256132 A JPH01256132 A JP H01256132A
Authority
JP
Japan
Prior art keywords
semiconductor element
electrode layer
substrate
semiconductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63084351A
Other languages
Japanese (ja)
Inventor
Hiroshi Noguchi
博司 野口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP63084351A priority Critical patent/JPH01256132A/en
Publication of JPH01256132A publication Critical patent/JPH01256132A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)

Abstract

PURPOSE:To enable the manufacturing of a semiconductor device without using solder material chip, and improve workability, by forming an electrode layer composed of solder material, on the rear of a semiconductor element, and mounting it on a necessary part of a substrate by fusion bonding of the electrode layer. CONSTITUTION:A thin film 5 of eutectic solder material is formed on the whole rear of a semiconductor wafer 1, on one surface of which semiconductor elements 2,... are formed. The wafer are broken along scribe trenches, and each semiconductor element 2 is separated. The whole rear of the separated semiconductor element 2 is covered with a thin film of eutectic solder material, and this thin film turns to an electrode layer 3 of each semiconductor element 2. This semiconductor element 2 is so mounted at a specified position of the substrate 4 that the electrode layer 3 faces downward. By fusion bonding treatment like thermal compression bonding, the electrode layer 3 is melted, and the semiconductor element 2 and the substrate 4 are electrically connected. Thereby, a process to interpose a solder chip between the semiconductor element 2 and the substrate 4 is saved, so that the mounting process of semiconductor elements is simplified, and workability is improved.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、主として高周波用の半導体装置の製造方法に
係り、詳しくは、半導体素子をセラミック基板やリード
フレームなどの基板へ実装する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention mainly relates to a method of manufacturing a high frequency semiconductor device, and more particularly to a method of mounting a semiconductor element on a substrate such as a ceramic substrate or a lead frame.

〈従来の技術〉 従来の半導体装置の製造方法を第4図に示す高周波用半
導体装置の製造方法に基づいて説明する。
<Prior Art> A conventional method for manufacturing a semiconductor device will be described based on a method for manufacturing a high frequency semiconductor device shown in FIG.

一般に高周波用半導体装置20は、裏面に金の蒸着など
によって電極21が形成された半導体素子22を基板2
3上に実装してつくられる。このとき、基板23と半導
体素子22との間には、Au −S i、Au −S 
n等の共晶ろう材チップ25が介装され、この共晶ろう
材チップ25の溶着によって基板23に半導体素子22
が固定されるとともに、半導体素子22の電極21と基
板23とが電気的に接続される。
Generally, the high-frequency semiconductor device 20 includes a semiconductor element 22 on which an electrode 21 is formed by vapor deposition of gold on the back surface of the substrate.
It is created by implementing it on top of 3. At this time, between the substrate 23 and the semiconductor element 22, Au-Si, Au-S
A eutectic brazing material chip 25 such as n is interposed, and the semiconductor element 22 is attached to the substrate 23 by welding the eutectic brazing material chip 25.
is fixed, and the electrode 21 of the semiconductor element 22 and the substrate 23 are electrically connected.

〈発明が解決しようとする課題〉 ところで、従来の高周波用半導体装置20の製造方法で
は、半導体素子22を基板23に実装するのに、上記し
たように共晶ろう材チップ25を用いており、この共晶
ろう材チップ25を正確に半導体素子22と基板23と
の間に挟み込む工程が必要であるため、それだけ作業が
複雑となり、容易に作業性の向上を図れなかった。
<Problems to be Solved by the Invention> By the way, in the conventional manufacturing method of the high frequency semiconductor device 20, the eutectic brazing material chip 25 is used as described above to mount the semiconductor element 22 on the substrate 23. Since a step of accurately sandwiching the eutectic brazing material chip 25 between the semiconductor element 22 and the substrate 23 is required, the work becomes more complicated and the workability cannot be easily improved.

また、基板との接続を確実にするためには充分な大きさ
のろう材チップ25を用いる必要があるが、このろう材
チップ25が大きいと、第5図に示すように、余分なろ
う材によって実装した半導体素子22が傾いて、後のワ
イヤボンディングに支障が生じたり、あるいは、ろう材
が半導体素子22からはみ出して短絡が生したりするこ
とがあり、高周波用半導体装置20の信頼性向上の妨げ
となっていた。
In addition, it is necessary to use a sufficiently large brazing material chip 25 to ensure the connection with the board, but if this brazing material chip 25 is large, as shown in FIG. This may cause the mounted semiconductor element 22 to be tilted, causing trouble in later wire bonding, or the brazing filler metal may protrude from the semiconductor element 22, causing a short circuit, thereby improving the reliability of the high frequency semiconductor device 20. It was a hindrance.

また、高価なろう材を多く使用することになるので、材
料コストがかさむという問題もある。
Furthermore, since a large amount of expensive brazing filler metal is used, there is also the problem that the material cost increases.

本発明は、上述の課題に鑑みてなされたものであって、
ろう材チップを用いることなく半導体装置を製造するこ
とができるようにして、作業性を良好にするとともに半
導体装置の信頼性を高めることを目的とする。
The present invention has been made in view of the above-mentioned problems, and includes:
It is an object of the present invention to make it possible to manufacture a semiconductor device without using a brazing material chip, thereby improving workability and increasing the reliability of the semiconductor device.

〈課題を解決するための手段〉 本発明は、上記の目的を達成するために、半導体素子の
裏面にろう材からなる電極層を形成する工程と、この半
導体素子を前記電極層の溶着により基板の所要部上に実
装する工程とを含むことに特徴を有している。
<Means for Solving the Problems> In order to achieve the above object, the present invention includes a step of forming an electrode layer made of a brazing material on the back surface of a semiconductor element, and a process of forming an electrode layer made of a brazing material on the back surface of a semiconductor element, and bonding the semiconductor element to a substrate by welding the electrode layer. The method is characterized in that it includes a step of mounting on a required portion of the device.

〈作用〉 上記製造方法によれば、ろう材を半導体素子の裏面に直
接電極層として設けであるので、半導体素子を直接に基
板の定位置に載置して熱圧着等の溶着処理をするだけで
実装できるようになり、従来のようなろう材チップを用
いる必要はなくなる。
<Function> According to the above manufacturing method, since the brazing material is directly provided as an electrode layer on the back surface of the semiconductor element, the semiconductor element is simply placed in a fixed position on the substrate and a welding process such as thermocompression bonding is performed. This eliminates the need to use brazing filler metal chips as in the past.

〈実施例〉 以下、本発明を第1図ないし第3図に示す高周波用半導
体装置の製造方法に基づいて詳細に説明する。これらの
図において、符号1は半導体ウェハ、2は高周波用半導
体素子、3は半導体素子2の電極層、4は基板である。
<Example> Hereinafter, the present invention will be explained in detail based on the method of manufacturing a high frequency semiconductor device shown in FIGS. 1 to 3. In these figures, numeral 1 is a semiconductor wafer, 2 is a high frequency semiconductor element, 3 is an electrode layer of the semiconductor element 2, and 4 is a substrate.

まず、第1図に示すように、−面に半導体素子2、・・
が形成された半導体ウェハ!の裏面全体に、真空蒸着処
理によりAu−5i、あるいはA u −S n等の共
晶ろう材の薄膜5を形成する。
First, as shown in FIG. 1, a semiconductor element 2,...
Semiconductor wafer formed with! A thin film 5 of a eutectic brazing material such as Au-5i or Au-Sn is formed on the entire back surface of the substrate by vacuum evaporation.

次に、第2図に示すように、このウェハlをスクライブ
溝に沿ってブレークし、各半導体素子2ごとに分離する
。分離された半導体素子2Cよその裏面全体が共晶ろう
材の薄膜によって覆われており、この薄膜が各半導体素
子2の電極層3になっている。
Next, as shown in FIG. 2, this wafer 1 is broken along the scribe grooves to separate each semiconductor element 2. The entire back surface of the separated semiconductor elements 2C is covered with a thin film of eutectic brazing material, and this thin film serves as the electrode layer 3 of each semiconductor element 2.

そして、この半導体素子2を電極層3を下にして基板4
の所定位置上に載置するとともに、熱圧着等の溶着処理
により、電極層3を溶融させて、この溶融した電極層3
により、半導体素子2を固定し、半導体素子2と基板4
とを電気的に接続させる。
Then, this semiconductor element 2 is placed on a substrate 4 with the electrode layer 3 facing down.
The electrode layer 3 is placed on a predetermined position, and the electrode layer 3 is melted by a welding process such as thermocompression bonding.
, the semiconductor element 2 is fixed and the semiconductor element 2 and the substrate 4 are fixed.
to be electrically connected.

上記の実施例においては、ろう材として共晶ろう材を用
いたが、他のろう材を用いてもよい。また実施例では、
ろう材を真空蒸着により薄膜の電極層3として、半導体
素子2の裏面に形成したが、ろう材を印刷により厚膜の
電極層として半導体素子の裏面に形成してもよい。
In the above embodiments, a eutectic brazing filler metal is used as the brazing filler metal, but other brazing filler metals may be used. In addition, in the example,
Although the brazing material is formed as a thin film electrode layer 3 on the back surface of the semiconductor element 2 by vacuum deposition, the brazing material may be formed as a thick film electrode layer on the back surface of the semiconductor element by printing.

また、上記の実施例は、高周波用半導体装置の製造方法
について説明したが、これに限らず、池の半導体装置の
製造方法についても実施できることはいうまでもない。
In addition, although the above-mentioned embodiment describes a method for manufacturing a high-frequency semiconductor device, the present invention is not limited to this, and it goes without saying that a method for manufacturing a semiconductor device can also be implemented.

〈発明の効果〉 以上のように、本発明の半導体装置の製造方法によれば
、ろう材を半導体素子の裏面に直接電極層として設けた
ので、従来のようなろう材デツプを用いなくても、半導
体素子を基板に実装することができる。したがって、ろ
う材チップを半導体素子と基板との間に介装する工程が
なくなるので、半導体素子の実装工程を簡略化でき、作
業性が向上する。
<Effects of the Invention> As described above, according to the method for manufacturing a semiconductor device of the present invention, since the brazing material is provided directly as an electrode layer on the back surface of the semiconductor element, there is no need to use a brazing material depth as in the conventional method. , a semiconductor element can be mounted on a substrate. Therefore, since there is no need to interpose the brazing material chip between the semiconductor element and the substrate, the process of mounting the semiconductor element can be simplified and work efficiency can be improved.

また、ろう材は半導体素子の裏面全面に膜状に設けられ
ているので、少量で必要量のろう材が素子と基板との間
に介在することになり、従来方法におけるような半導体
素子の傾きやろう材のはみ出しを未然に防止して、これ
らに起因する不都合の発生をなくすことができ、半導体
装置の信頼性は向上する。また、ろう材の使用催を少量
に抑えることができ、材料コストの低減を図ることがで
きる。
In addition, since the brazing material is provided in a film form over the entire back surface of the semiconductor element, a small but necessary amount of the brazing material is interposed between the element and the substrate, which prevents the semiconductor element from tilting as in the conventional method. It is possible to prevent the brazing filler metal from protruding, thereby eliminating inconveniences caused by this, and improving the reliability of the semiconductor device. Further, the amount of brazing filler metal used can be kept to a small amount, and material costs can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第3図は本発明の一実施例の高周波用半導
体装置の製造工程を示し、第1図と第2図とは側面図、
第3図は斜視図である。第4図と第5図とは従来例に係
り、第4図は高周波用半導体装置の製造工程を表す斜視
図、第5図はその断面図である。 2・・半導体素子、3・・電極層、4・・・基板、出願
人  法式会社 材用製作所 代理人  弁理士  岡1)和秀 第1図 第2図 第3図
1 to 3 show the manufacturing process of a high frequency semiconductor device according to an embodiment of the present invention, and FIGS. 1 and 2 are side views,
FIG. 3 is a perspective view. 4 and 5 relate to a conventional example, where FIG. 4 is a perspective view showing the manufacturing process of a high frequency semiconductor device, and FIG. 5 is a sectional view thereof. 2...Semiconductor element, 3...Electrode layer, 4...Substrate, Applicant Legal company Material manufacturing agent Patent attorney Oka 1) Kazuhide Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] (1)半導体素子の裏面にろう材からなる電極層を形成
する工程と、 この半導体素子を前記電極層の溶着により基板の所要部
上に実装する工程とを含むことを特徴とする半導体装置
の製造方法。
(1) A semiconductor device characterized by comprising a step of forming an electrode layer made of a brazing material on the back surface of a semiconductor element, and a step of mounting the semiconductor element on a desired part of a substrate by welding the electrode layer. Production method.
JP63084351A 1988-04-05 1988-04-05 Manufacture of semiconductor device Pending JPH01256132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63084351A JPH01256132A (en) 1988-04-05 1988-04-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63084351A JPH01256132A (en) 1988-04-05 1988-04-05 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01256132A true JPH01256132A (en) 1989-10-12

Family

ID=13828099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63084351A Pending JPH01256132A (en) 1988-04-05 1988-04-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01256132A (en)

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