JPH01260537A - Equipment control processor circuit - Google Patents

Abstract

PURPOSE:To generate a subroutine whose bank switching is required without being conscious of the description of a program by generating an interruption signal at the time of detecting a specific first instruction code decided in advance, and storing the number of addresses exceeding the address space of a microprocessor. CONSTITUTION:The title circuit is constituted of the microprocessor 1, a bank register 2, a program memory 3, a control memory 4, an instruction detection circuit 5, and an interruption control circuit 6. And the instruction detection circuit 5 generates the interruption signal (c) at the time of detecting a prescribed first instruction code decided in advance, and the bank register 2 stores the address exceeding the address space of the microprocessor. In such a way, it is possible to perform the bank switching automatically without being conscious of the bank switching in the description of the program.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an equipment control processor circuit using a microprocessor, and particularly to an equipment control processor circuit that is larger than the address space of the control program or processor.

[Conventional technology]

Conventionally, when a control program is larger than the processor address space, it has been necessary for each module of the control program to switch banks of the program itself.

[Problem to be solved by the invention]

For this reason, when creating a program, one must always be aware of bank switching, which has the disadvantage of reducing the efficiency of program creation or reducing the versatility of the program.

An object of the present invention is to provide a control processor that automatically performs bank switching without being aware of bank switching in program description.

[Means to solve the problem]

According to the present invention, in a device control processor mainly composed of a microprocessor, an instruction detection circuit that generates an interrupt signal when a predetermined specific first instruction code is not detected; An equipment control processor circuit is obtained having a bank register for storing addresses of .

〔Example〕

Next, the present invention will be described in more detail with reference to the drawings showing one embodiment of the present invention.

Referring to FIG. 1, one embodiment of the present invention consists of a microprocessor 1, a bank register 2, a program memory 3, a control memory 4, an instruction detection circuit 5, and an interrupt control circuit 6. ing. In this embodiment, Indel's J8080 is used as the microprocessor 1.

Figure 2 shows the machine language of the program that calls address O]00, which requires bank switching, and Figure 3 shows the machine language that calls address 012345, which requires bank switching. FIG. The linker will process whether bank switching is necessary, and if bank switching is necessary, that is, if the top height of the address changes,
A machine code is generated by replacing the instruction code 1~ with a predetermined code (=J. Here, the specific code 1- is E l',
) ], hex “C”.

FIG. 4 is a flowchart showing the operation of the programmer 11 when bank switching is required.

If bank switching is required, the first command yaw 1~ is ED
Since it is in hexadecimal format, when the microprocessor 1 or 2 reads an instruction, an interrupt signal C is generated from the instruction detection circuit 5, a call instruction is generated from the interrupt control circuit 6, and predetermined interrupt processing is performed. Operate. At this time, if no interrupt occurs, the address next to the address is saved to the stack.

In the interrupt processing J1, as shown in the 4th [YH], the address and 3 bytes of hunk data of the uncalled subroutine are extracted from the address next to the address where the first interrupt occurred, and after saving, the next Save Aljeres to the stack.

Next, save the current bank to the stack 7, and save the start address of the termination processing routine to be executed when returning from the subroutine called next to the stack.
Place the call saved in f to the top of the routine that should be placed in the bank register, and set the bottom 2 in the bank register.
Call Zabroutine with Hyde as Aljeres.

After the subroutine performs its predetermined operations, the user returns and control returns to the termination routine that was previously saved to the stack.

The termination processing routine takes out the bank saved before the subroutine call from the stack, stores it in the 7 bank register, and then returns. This returns the program to the next routine call that requires profurano\ switching.

In the embodiments described above, the instruction detection circuit 5 is provided so that it can be realized with a general microprocessor. In this case, it goes without saying that the instruction detection [n path is unnecessary.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to create subroutines that are necessary for bank switching without having to be aware of the program description.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing machine language when J bank switching is not required, and FIG. 3 is a diagram showing machine language when bank switching is required. , Fig. 4 shows the operation flowchart 1 to 1 when bank switching is required. 1. Microprocessor, 2. Bank register, 3. Program memory, 4. Control memory, 5. Instruction detection circuit, 6.
・Interrupt control circuit. and 1 address signal, g) data, and C interrupt signal.

Claims (1)

[Claims] In an equipment control processor mainly composed of a microprocessor, there is an instruction detection circuit that generates an interrupt signal when a predetermined specific first instruction code is detected, and a bank register that stores addresses larger than the address space of the microprocessor. An equipment control processor circuit comprising: