JPH0126101B2 - - Google Patents

Info

Publication number
JPH0126101B2
JPH0126101B2 JP58189722A JP18972283A JPH0126101B2 JP H0126101 B2 JPH0126101 B2 JP H0126101B2 JP 58189722 A JP58189722 A JP 58189722A JP 18972283 A JP18972283 A JP 18972283A JP H0126101 B2 JPH0126101 B2 JP H0126101B2
Authority
JP
Japan
Prior art keywords
data
permutation
bits
subblock
row
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58189722A
Other languages
English (en)
Other versions
JPS6081661A (ja
Inventor
Yasukazu Nishino
Hiroshi Sasanuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58189722A priority Critical patent/JPS6081661A/ja
Publication of JPS6081661A publication Critical patent/JPS6081661A/ja
Publication of JPH0126101B2 publication Critical patent/JPH0126101B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Image Input (AREA)
  • Image Processing (AREA)

Claims (1)

    【特許請求の範囲】
  1. １ 2n1個のデータの総ての2l+1・ｉ−2l−ｊ番目
    のデータと2l+1・ｉ−ｊ第目のデータを入れ換え
    る置換をP2l、相異なる置換P2lを引続き行なつて
    得られる合成の置換をPn及びデータの入れ換え
    を行なわない恒等置換をP0とした時に得られる
    総ての置換Pkを置換集合の要素とした時、行方
    向、列方向にそれぞれ2n1+2nビツトで構成された
    ブロツク内におけるデータを行方向、列方向にそ
    れぞれ2n1ビツトごとに区切り、2n1×2n1ビツトの
    データで一つのサブブロツクを構成し、サブブロ
    ツク内における行方向（或いは列方向）の2n1ビ
    ツトの入力データに対してサブブロツクがブロツ
    ク内で占める位置に対応させて、前記置換集合の
    要素をP0から順に並べたP0，P1，P2，…，P2o1-1
    に前記手法の置換Pkの一つを施して各置換の順
    番を定め、順番が定められた置換と前記入力デー
    タのサブブロツク内での行（列）番号とを順に対
    応させて入力データの並び換えを行なう手段と、
    前記並び換えを行なつた入力データを記憶する独
    立に動作可能な2n1個のメモリm1，m2，…m2o1を
    有し、前記2n1個の各メモリのアドレス入力a0，
    a1，…，ao1-1のn1本に関しては、メモリ
    m2l+1
JP58189722A 1983-10-11 1983-10-11 デ−タ記憶装置 Granted JPS6081661A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58189722A JPS6081661A (ja) 1983-10-11 1983-10-11 デ−タ記憶装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58189722A JPS6081661A (ja) 1983-10-11 1983-10-11 デ−タ記憶装置

Publications (2)

Publication Number Publication Date
JPS6081661A JPS6081661A (ja) 1985-05-09
JPH0126101B2 true JPH0126101B2 (ja) 1989-05-22

Family

ID=16246091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58189722A Granted JPS6081661A (ja) 1983-10-11 1983-10-11 デ−タ記憶装置

Country Status (1)

Country Link
JP (1) JPS6081661A (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62988A (ja) * 1985-02-27 1987-01-06 大日本スクリ−ン製造株式会社 画像デ−タの表示方法
JPS62262187A (ja) * 1986-05-08 1987-11-14 Matsushita Electric Ind Co Ltd メモリ装置

Also Published As

Publication number Publication date
JPS6081661A (ja) 1985-05-09

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