JPH0126533B2 - - Google Patents
Info
- Publication number
- JPH0126533B2 JPH0126533B2 JP57080389A JP8038982A JPH0126533B2 JP H0126533 B2 JPH0126533 B2 JP H0126533B2 JP 57080389 A JP57080389 A JP 57080389A JP 8038982 A JP8038982 A JP 8038982A JP H0126533 B2 JPH0126533 B2 JP H0126533B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- polycrystalline silicon
- bonding pad
- metal layer
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/923—Bond pads having multiple stacked layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/981—Auxiliary members, e.g. spacers
- H10W72/983—Reinforcing structures, e.g. collars
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の電極構造に関し、特に外
部端子とペレツトを金属線にて接続するためのペ
レツト側のボンデイングパツドの構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrode structure of a semiconductor device, and more particularly to a structure of a bonding pad on a pellet side for connecting an external terminal and a pellet with a metal wire.
従来、ペレツトのボンデイングパツドは第1図
aに示すように、基板1上に形成された酸化膜2
の上にアルミニウム配線3と、これに連続するア
ルミニウム電極4とを同時に形成し、パツシベー
シヨンとして絶縁物5,5′等を形成し、アルミ
ニウム電極4を露出してボンデイングパツドとし
て用い、ここにアルミニウムもしくは金線等の金
属線6を用いてボンデイングを行い、外部端子と
の接続を取つていた。この構造の場合、ペレツト
上に水分が付着した状態で長時間(例えば数1000
時間)使用状態を続けると、金属線6周辺のボン
デイングパツドが露光しているためにアルミニウ
ムのイオン化係数が大きいことも手伝つて水分中
にAl3+イオンとして溶け込み、この部分のアル
ミニウム電極4に第2図bの7,7′に示すよう
な穴があき、アルミ電極4とアルミ配線3とが電
気的に開放状態となることがあつた。 Conventionally, a pellet bonding pad is made of an oxide film 2 formed on a substrate 1, as shown in FIG.
On top of this, an aluminum wiring 3 and an aluminum electrode 4 continuous thereto are simultaneously formed, insulators 5, 5', etc. are formed as passivation, and the aluminum electrode 4 is exposed and used as a bonding pad. Alternatively, a metal wire 6 such as a gold wire is used to perform bonding to establish a connection with an external terminal. In the case of this structure, the moisture remains on the pellet for a long period of time (for example, several thousand
As the bonding pad around the metal wire 6 is exposed to light, aluminum has a large ionization coefficient, and as a result, it dissolves into moisture as Al 3+ ions, and the aluminum electrode 4 in this area dissolves into the moisture. In some cases, holes as shown at 7 and 7' in FIG. 2b were formed in the aluminum electrode 4 and the aluminum wiring 3 became electrically open.
本発明はボンデイングパツド露出部分から浸入
する水分に対してボンデイングパツドとこれに連
続する配線属との間で断線が生じない構造の半導
体装置を提供することを目的とする。本発明の半
導体装置は、半導体基板上に設けられた第1の絶
縁膜と、前記第1の絶縁膜上に設けられ、電極部
分及びこの電極部分の一部に連続して導出された
配線部分を有する金属層と、前記第1の絶縁膜及
び前記金属層を覆う第2の絶縁膜とを有し、前記
第2の絶縁膜に設けられた開孔部により前記金属
層の前記電極部分の一部が露出され、当該露出部
分をボンデイングパツドとして用いる半導体装置
において、前記電極部分の前記ボンデイングパツ
ド部分と前記第1の絶縁膜との間に不純物がドー
プされた低抵抗率の多結晶シリコン層を前記ボン
デイングパツド部分に接触して設け、かつ前記多
結晶シリコン層は、前記金属層の前記第2の絶縁
膜で覆われた部分の下を経て前記配線部側に延在
形成されていて前記配線部に電気的に接続されて
いることを特徴とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a structure that prevents disconnection between a bonding pad and a wiring connected thereto due to moisture infiltrating from an exposed portion of the bonding pad. The semiconductor device of the present invention includes a first insulating film provided on a semiconductor substrate, an electrode portion provided on the first insulating film, and a wiring portion continuously led out to a part of the electrode portion. and a second insulating film that covers the first insulating film and the metal layer, and an opening provided in the second insulating film allows the electrode portion of the metal layer to be In a semiconductor device in which a portion of the electrode portion is exposed and the exposed portion is used as a bonding pad, a low resistivity polycrystal doped with an impurity is provided between the bonding pad portion of the electrode portion and the first insulating film. A silicon layer is provided in contact with the bonding pad portion, and the polycrystalline silicon layer is formed to extend toward the wiring portion through a portion of the metal layer covered with the second insulating film. The wire is electrically connected to the wiring portion.
以下図面を用いて本発明の一実施例を詳細に説
明する。 An embodiment of the present invention will be described in detail below with reference to the drawings.
第2図aに示すように基板1上に形成された酸
化膜2の上に不純物をドープされた低抵抗率の多
結晶シリコン8を5000Å程度形成し、アルミニウ
ム配線3とアルミニウム電極4を1〜2μm程度同
時に連続して形成する。その後パツシベーシヨン
として絶縁物5,5′を形成する。多結晶シリコ
ン8とアルミニウム電極4およびアルミニウム配
線3は電気的に接続されていなければならない。 As shown in FIG. 2a, on the oxide film 2 formed on the substrate 1, a polycrystalline silicon 8 doped with impurities and having a low resistivity of about 5000 Å is formed, and an aluminum wiring 3 and an aluminum electrode 4 are formed on the oxide film 2. Continuously form about 2 μm at the same time. Thereafter, insulators 5 and 5' are formed as passivations. Polycrystalline silicon 8, aluminum electrode 4, and aluminum wiring 3 must be electrically connected.
以上のような構造の場合、ベレツト上に水分が
付着した状態で長時間使用状態を読けることによ
つて従来の構造と同様に第2図bに示すように
7,7′の穴があき、アルミニウム電極4とアル
ミニウム配線3との間が断線しても、導電通路は
多結晶シリコンを介して形成されており、しかも
この多結晶シリコンは、水分中に溶け込まないた
め、9,9′の点以上には穴はあかない。従つて、
アルミニウム電極4―多結晶シリコン8―アルミ
ニウム配線3の経路で電気的に接続され、断線事
故は発生しない。 In the case of the above structure, holes 7 and 7' are formed as shown in Figure 2b, similar to the conventional structure, so that the state of use for a long time can be read with moisture attached to the beret. Even if there is a disconnection between the aluminum electrode 4 and the aluminum wiring 3, the conductive path is formed through polycrystalline silicon, and this polycrystalline silicon does not dissolve in moisture. No holes will be made beyond the point. Therefore,
Electrical connection is made through the route of aluminum electrode 4 - polycrystalline silicon 8 - aluminum wiring 3, and no disconnection accidents occur.
更に、図面より明らかのように、パツド下に設
けた低抵抗率の多結晶シリコン層8は第2の絶縁
膜5′で覆われた金属層4,3の部分の下を経て
配線側に延在形成している。この構成によれば、
第2の絶縁膜5′に設けられたパツド形成用開孔
部のエツジでの金属層はその内部においても所期
の厚さを保つことになり、浸入した水分によつて
金属層が多少腐食されても多結晶シリコン層上に
はまだ充分な厚さをもつて残り、かつ多結晶シリ
コンと配線との充分な接触面積も得ることがで
る。従つて、パツドと配線との接続を充分小さい
電気的抵抗をもつて保つことが可能となる。 Furthermore, as is clear from the drawing, the low-resistivity polycrystalline silicon layer 8 provided under the pad extends to the wiring side through the portions of the metal layers 4 and 3 covered with the second insulating film 5'. It is currently forming. According to this configuration,
The metal layer at the edge of the opening for pad formation provided in the second insulating film 5' maintains the desired thickness even inside, and the metal layer is slightly corroded by the moisture that has entered. Even if the polycrystalline silicon layer is removed, a sufficient thickness remains on the polycrystalline silicon layer, and a sufficient contact area between the polycrystalline silicon and the wiring can be obtained. Therefore, it is possible to maintain the connection between the pad and the wiring with a sufficiently low electrical resistance.
また、本構造の多結晶シリコンは、これを用い
て多層配線、多結晶シリコン抵抗等を形成する場
合に同時に形成できるため、特に工程を追加する
必要もなく、簡単に形成できるという長所を持つ
ている。さらに多結晶シリコンには、どのような
不純物をドープしても問題はなく、ドープされた
多結晶シリコンを成長させても多結晶シリコンに
イオン注入、拡散等で不純物をドープしても問題
はない。即ち、簡単に導電層とすることができ
る。 In addition, the polycrystalline silicon of this structure can be used to form multilayer wiring, polycrystalline silicon resistance, etc. at the same time, so it has the advantage of being easy to form without the need for any additional steps. There is. Furthermore, there is no problem with doping polycrystalline silicon with any kind of impurity, and there is no problem even if doped polycrystalline silicon is grown or polycrystalline silicon is doped with impurities by ion implantation, diffusion, etc. . That is, it can be easily made into a conductive layer.
なお、多結晶シリコンはボンデイングパツドと
配線層との間に位置する部分の直下にさえ設けて
おけばよい。 Note that it is sufficient to provide the polycrystalline silicon just below the portion located between the bonding pad and the wiring layer.
第1図aは従来のボンデングパツドの断面構造
図、bは従来の構造でアルミニウムが水分中に溶
け込み断線した状態図を示す断面図、第2図aは
本発明の一実施例によるボンデイングパツド部の
断面構造図、bは本発明の構造で、アルミニウム
が水分中に溶け込み、アルミニウムのみ断線した
時の状態を示す断面図である。
1……半導体基板、2……酸化膜、3……アル
ミニウム配線層、4……アルミニウム電極(ボン
デイングパツド)、5,5′……絶縁膜、6……ボ
ンデイング線、7,7′……腐食による開孔、8
……多結晶シリコン。
Fig. 1a is a cross-sectional structural diagram of a conventional bonding pad, b is a cross-sectional view showing a conventional structure in which aluminum dissolves in moisture and the wire is broken, and Fig. 2a is a bonding pad according to an embodiment of the present invention. Fig. 2B is a cross-sectional view showing the structure of the present invention when aluminum dissolves in moisture and only the aluminum is disconnected. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Oxide film, 3... Aluminum wiring layer, 4... Aluminum electrode (bonding pad), 5, 5'... Insulating film, 6... Bonding line, 7, 7'... ...Opening due to corrosion, 8
...Polycrystalline silicon.
Claims (1)
前記第1の絶縁膜上に設けられ、電極部分及びこ
の電極部分の一部に連続して導出された配線部分
を有する金属層と、前記第1の絶縁膜及び前記金
属層を覆う第2の絶縁膜とを有し、前記第2の絶
縁膜に設けられた開孔部により前記金属層の前記
電極部分の一部が露出され、当該露出部分をボン
デイングパツドとして用いる半導体装置におい
て、前記電極部分の前記ボンデイングパツド部分
と前記第1の絶縁膜との間に不純物がドープされ
た低抵抗率の多結晶シリコン層を前記ボンデイン
グパツド部分に接触して設け、かつ前記多結晶シ
リコン層は、前記金属層の前記第2の絶縁膜で覆
われた部分の下を経て前記配線部側に延在形成さ
れていて前記配線部に電気的に接続されているこ
とを特徴とする半導体装置。1 a first insulating film provided on a semiconductor substrate;
a metal layer provided on the first insulating film and having an electrode portion and a wiring portion continuous to a part of the electrode portion; and a second metal layer covering the first insulating film and the metal layer. an insulating film, a part of the electrode part of the metal layer is exposed through an opening provided in the second insulating film, and the exposed part is used as a bonding pad. A polycrystalline silicon layer doped with impurities and having a low resistivity is provided between the bonding pad portion and the first insulating film in contact with the bonding pad portion, and the polycrystalline silicon layer is . A semiconductor device, characterized in that the metal layer is formed to extend toward the wiring section through a portion covered with the second insulating film, and is electrically connected to the wiring section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57080389A JPS58197736A (en) | 1982-05-13 | 1982-05-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57080389A JPS58197736A (en) | 1982-05-13 | 1982-05-13 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58197736A JPS58197736A (en) | 1983-11-17 |
| JPH0126533B2 true JPH0126533B2 (en) | 1989-05-24 |
Family
ID=13716928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57080389A Granted JPS58197736A (en) | 1982-05-13 | 1982-05-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58197736A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2641998B2 (en) * | 1991-03-20 | 1997-08-20 | ローム 株式会社 | Semiconductor device |
| TW318321B (en) | 1995-07-14 | 1997-10-21 | Matsushita Electric Industrial Co Ltd |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5239378A (en) * | 1975-09-23 | 1977-03-26 | Seiko Epson Corp | Silicon-gated mos type semiconductor device |
| JPS55140245A (en) * | 1979-04-18 | 1980-11-01 | Fujitsu Ltd | Manufacture of semiconductor element |
-
1982
- 1982-05-13 JP JP57080389A patent/JPS58197736A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58197736A (en) | 1983-11-17 |
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