JPH0126576B2 - - Google Patents

Info

Publication number
JPH0126576B2
JPH0126576B2 JP10388283A JP10388283A JPH0126576B2 JP H0126576 B2 JPH0126576 B2 JP H0126576B2 JP 10388283 A JP10388283 A JP 10388283A JP 10388283 A JP10388283 A JP 10388283A JP H0126576 B2 JPH0126576 B2 JP H0126576B2
Authority
JP
Japan
Prior art keywords
transmission line
signal
add
terminal
drop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10388283A
Other languages
Japanese (ja)
Other versions
JPS59229943A (en
Inventor
Koichi Ooyama
Tomohiro Shirakawa
Masaaki Yokoyama
Hisao Uose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Iwasaki Tsushinki KK
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Iwasaki Tsushinki KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Iwasaki Tsushinki KK filed Critical Nippon Telegraph and Telephone Corp
Priority to JP10388283A priority Critical patent/JPS59229943A/en
Publication of JPS59229943A publication Critical patent/JPS59229943A/en
Publication of JPH0126576B2 publication Critical patent/JPH0126576B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/08—Intermediate station arrangements, e.g. for branching, for tapping-off

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Dc Digital Transmission (AREA)

Description

【発明の詳細な説明】 本発明はデイジタル化された多重加入者系の分
岐挿入装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digitized multi-subscriber add/drop device.

従来、この種の多重加入者系としては、多重伝
送路を各端末に引き込み、他端末からのデータも
端末内で再生中継する構成が知られていたが、こ
の構成では一つでも端末に障害が発生したり、端
末と伝送路の接続部分周辺に切断等の障害が発生
した場合には、他端末の通信も不可能となる欠点
があつた。 Conventionally, this type of multi-subscriber system has been known to have a configuration in which multiple transmission paths are drawn into each terminal and data from other terminals is also regenerated and relayed within the terminal, but with this configuration even one terminal has a failure. If a fault occurs such as a disconnection or the like in the vicinity of the connection between the terminal and the transmission line, communication with other terminals becomes impossible.

この欠点を解決する方式として、複数の端末を
分岐挿入装置を介して多重伝送路に時分割多重化
して収容し、多重伝送路及び端末から分岐挿入装
置までの伝送路の無通話チヤネルのビツトパタン
を全て論理値“１”とし、上記分岐挿入装置の挿
入回路を論理積ゲートで構成し、その分岐挿入装
置の端末側挿入部にエラステイツクストアを用い
たフレーム同期化回路を設け、上記端末から分岐
挿入装置までの伝送路が開放状態となつた時、そ
の分岐挿入装置の端末側挿入部の入力を強制的に
論理値“１”にする伝送路終端回路を設ける方式
が、本願出願人の一人により特願昭57−205427号
「多重加入者系分岐挿入方式」として提案されて
いる。 As a method to solve this drawback, multiple terminals are time-division multiplexed and accommodated on multiple transmission paths via drop/add devices, and the bit pattern of the silent channel of the multiple transmission path and the transmission path from the terminals to the add/drop device is changed. All the logic values are set to "1", and the insertion circuit of the above-mentioned drop-and-insert device is configured with an AND gate, and a frame synchronization circuit using an elastic store is provided in the terminal-side insertion section of the branch-and-insert device, and the One of the applicants of this application has proposed a method in which a transmission line termination circuit is provided that forcibly sets the input of the terminal-side insertion section of the add-drop device to a logical value of "1" when the transmission path to the insertion device becomes open. It has been proposed in Japanese Patent Application No. 57-205427 as ``Multiple subscriber system drop/add system''.

本発明は、前記多重加入者系分岐挿入方式を用
いた分岐挿入装置の障害時の動作をさらに完全な
ものとするため、端末から分岐挿入装置までの伝
送路上の信号の状態遷移が一定時間以上存在しな
い場合に上記エラステイツクストアの出力を強制
的に論理値“１”または“０”の予め定めた一方
にする回路を設けるようにして端末等の障害の影
響が多重伝送路に波及しない高信頼度の加入者系
が構成可能となるようにしたもので、以下図面を
用いて詳細に説明する。 In order to further perfect the operation of a drop/add device using the multi-subscriber system when a failure occurs, the present invention provides that the state transition of a signal on a transmission path from a terminal to a drop/add device exceeds a certain period of time. By providing a circuit that forcibly sets the output of the elastic store to one of the predetermined logical values of "1" or "0" when the elastic store does not exist, it is possible to prevent the effects of failures in terminals, etc. from spreading to the multiplex transmission path. This system is designed so that a subscriber system of reliability can be configured, and will be explained in detail below using the drawings.

第１図は本発明を用いた多重加入者系のシステ
ム構成の一実施例を示し、１は地域内で生じる呼
の他対地への接続を行なう加入者系交換機、２は
端末から交換機への信号を伝送する上り多重伝送
路、３は交換機から端末への信号を伝送する下り
多重伝送路、４は多重伝送路２及び３へのチヤネ
ルアクセス機能を有する端末、５は下り多重伝送
路３のクロツクを抽出・再生して上り多重伝送路
２に供給する伝送路終端装置、６は多重伝送路の
信号を端末側の加入者伝送路に分岐し端末からの
信号を多重伝送路上に挿入する分岐挿入装置、７
は端末４から分岐挿入装置６へ信号を伝送する上
り加入者伝送路、８は分岐挿入装置６から端末４
へ信号を伝送する下り加入者伝送路である。 FIG. 1 shows an embodiment of a multi-subscriber system configuration using the present invention, in which 1 is a subscriber exchange that connects calls occurring within a region to other destinations, and 2 is a connection from a terminal to an exchange. 3 is an uplink multiplex transmission line for transmitting signals, 3 is a downlink multiplex transmission line for transmitting signals from the exchange to the terminal, 4 is a terminal having a channel access function to multiplex transmission lines 2 and 3, and 5 is a downstream multiplex transmission line for 3. A transmission line termination device extracts and regenerates the clock and supplies it to the uplink multiplex transmission line 2. 6 is a branch that branches the signal of the multiplex transmission line to the subscriber transmission line on the terminal side and inserts the signal from the terminal onto the multiplex transmission line. insertion device, 7
8 is an uplink subscriber transmission line that transmits signals from the terminal 4 to the drop/add device 6;
This is a downlink subscriber transmission line that transmits signals to.

なお、上り加入者伝送路７を介して端末４から
送出される信号と、上り多重伝送路２を介して加
入者系交換機１へ伝送される信号とは周波数は等
しいが位相は異なるものである。 Note that the signal sent from the terminal 4 via the uplink subscriber transmission line 7 and the signal transmitted to the subscriber exchange 1 via the uplink multiplex transmission line 2 have the same frequency but different phases. .

本構成において、多重伝送路２及び３と、加入
者伝送路７及び８の無通話チヤネルのビツトパタ
ンは全て論理値“１”とする。ここで無通話チヤ
ネルとは、多重伝送路２または３及び下り加入者
伝送路８においては、加入者交換機１及び加入者
系に接続されている全ての端末４が使用していな
い空チヤネルを意味し、上り加入者伝送路７にお
いては、その加入者伝送路に接続されている端末
が使用していないチヤネルを意味する。なお、伝
送路終端装置５は当然加入者交換機１より一番遠
い分岐挿入装置６に含めることも可能である。 In this configuration, the bit patterns of the non-call channels of multiplex transmission lines 2 and 3 and subscriber transmission lines 7 and 8 are all set to logical value "1". Here, a dead channel means an empty channel that is not used by the subscriber exchange 1 and all the terminals 4 connected to the subscriber system in the multiplex transmission line 2 or 3 and the downlink subscriber transmission line 8. However, in the uplink subscriber transmission line 7, it means a channel that is not used by a terminal connected to that subscriber transmission line. It should be noted that the transmission line termination device 5 can of course be included in the drop/add device 6 that is farthest from the subscriber exchange 1.

第２図は第１図における分岐挿入装置６の詳細
な構成を示す本発明による一実施例のブロツク図
であり、２−１は入り側の上り多重伝送路、２−
２は出側の上り多重伝送路、３−１は入り側の下
り多重伝送路、３−２は出側の下り多重伝送路、
７は上り加入者伝送路、８は下り加入者伝送路、
９，１４，１９は受信バツフア増幅器、１０，１
５，２０はクロツク抽出回路、１１，１６，２
１，２５はＤ形FF（フリツプフロツプ）回路、１
２，１３，２６は送信バツフア増幅器、１７，２
２はフレーム抽出回路、１８は伝送路終端抵抗、
２３はエラステイツクストア、２４は論理積ゲー
ト、２７は状態遷移検出回路、２８は論理和ゲー
トを示す。 FIG. 2 is a block diagram of an embodiment according to the present invention showing a detailed configuration of the add/drop drop device 6 in FIG.
2 is an uplink multiplex transmission line on the output side, 3-1 is a downlink multiplex transmission line on the input side, 3-2 is a downlink multiplex transmission line on the output side,
7 is an uplink subscriber transmission line, 8 is a downlink subscriber transmission line,
9, 14, 19 are receiving buffer amplifiers, 10, 1
5, 20 are clock extraction circuits, 11, 16, 2
1 and 25 are D-type FF (flip-flop) circuits, 1
2, 13, 26 are transmission buffer amplifiers, 17, 2
2 is a frame extraction circuit, 18 is a transmission line terminating resistor,
23 is an elastic store, 24 is an AND gate, 27 is a state transition detection circuit, and 28 is an OR gate.

第３図ａ〜ｌは第２図に示した分岐挿入装置の
各部ａ〜ｌにおける信号の一例を示すものであ
り、ａ〜ｌとａ〜ｌとはそれぞれ対応している。
また第４図ｃ，ｅ，ｆ，ｇ，ｌ，ｍ，ｎは第２図
に示した分岐挿入装置の各部ｃ，ｅ，ｆ，ｇ，
ｌ，ｍ，ｎにおける信号の障害時の一例を示すも
のであり、それぞれ対応している。 FIGS. 3a to 3 show examples of signals in each part a to l of the add/drop dropout device shown in FIG. 2, and a to l correspond to each other, respectively.
In addition, Fig. 4 c, e, f, g, l, m, and n are each part c, e, f, g,
This shows an example of a signal failure in l, m, and n, and corresponds to each other.

以下、第１図、第２図、第３図、及び第４図を
用いてその動作を説明する。 The operation will be described below with reference to FIGS. 1, 2, 3, and 4.

加入者系交換機１からの入り側下り多重伝送路
３−１の信号は受信バツフア増幅器９で受信さ
れ、波形整形後、クロツク抽出回路１０により発
生されたビツト同期信号を用いてＤ形FF回路１
１により波形再生を行ない、送信バツフア増幅器
１２を介して出側下り多重伝送路３−２へ再送を
行なうと共に、送信バツフア増幅器１３を介して
下り加入者伝送路８へ分岐を行なう。 The signal on the downlink multiplex transmission line 3-1 from the subscriber exchange 1 is received by the reception buffer amplifier 9, and after waveform shaping, the signal is sent to the D-type FF circuit 1 using the bit synchronization signal generated by the clock extraction circuit 10.
1, the waveform is regenerated and retransmitted to the outgoing downlink multiplex transmission line 3-2 via the transmission buffer amplifier 12, and branched to the downlink subscriber transmission line 8 via the transmission buffer amplifier 13.

加入者系交換機１へ向かう入り側上り多重伝送
路２−１の信号は受信バツフア増幅器１４で受信
され波形整形後、その信号ａはクロツク抽出回路
１５により発生したビツト同期信号ｃを用いてＤ
形FF回路１６により波形再生されて信号ｂが得
られる。フレーム抽出回路１７は、この信号ｂと
ビツト同期信号ｃからフレーム同期信号ｄを抽出
する。 The signal on the incoming uplink multiplex transmission line 2-1 heading toward the subscriber exchange 1 is received by the reception buffer amplifier 14, and after waveform shaping, the signal a is converted to D using the bit synchronization signal c generated by the clock extraction circuit 15.
The waveform is reproduced by the FF circuit 16 to obtain signal b. The frame extraction circuit 17 extracts a frame synchronization signal d from this signal b and the bit synchronization signal c.

上り加入者伝送路７の信号も同様に受信バツフ
ア増幅器１９で受け、その出力信号ｅはクロツク
抽出回路２０、Ｄ形FF回路２１、フレーム抽出
回路２２の各回路によりクロツク抽出、波形再
生、フレーム同期信号抽出が行なわれる。端末は
入り側下り多重伝送路３−１のクロツクにより動
作させ、端末障害時は自端末を自動的に加入者伝
送路から切り離す構成とする。 The signal on the uplink subscriber transmission line 7 is similarly received by the reception buffer amplifier 19, and its output signal e is subjected to clock extraction, waveform reproduction, and frame synchronization by the clock extraction circuit 20, the D-type FF circuit 21, and the frame extraction circuit 22. Signal extraction is performed. The terminal is operated by the clock of the incoming downlink multiplex transmission path 3-1, and is configured to automatically disconnect itself from the subscriber's transmission path in the event of a terminal failure.

Ｄ形FF回路２１により整形された信号ｆは、
フレーム抽出回路２２からのフレーム同期信号ｈ
によつて、エラステイツクストア２３の先頭番地
から、クロツク抽出回路２０により生成されたビ
ツト同期信号ｇの周期で蓄積される。 The signal f shaped by the D-type FF circuit 21 is
Frame synchronization signal h from frame extraction circuit 22
Accordingly, data is accumulated from the first address of the elastic store 23 at the cycle of the bit synchronization signal g generated by the clock extraction circuit 20.

エラステイツクストア２３からの読み出しは、
フレーム抽出回路１７のフレーム同期信号ｄによ
つて、クロツク抽出回路１５により生成されたビ
ツト同期信号ｃの周期で読み出される。これによ
り論理積ゲート２４の２入力、すなわち多重伝送
路の信号ｂと加入者伝送路の信号ｎ（障害が無い
時には信号ｉに等しい）のフレーム同期がとら
れ、従つて論理積ゲート２４の出力信号ｊには入
り側上り多重伝送路２−１と上り加入者伝送路７
の各々の同じチヤネル番号を持つ信号（チヤネル
番号は１つのフレーム内の信号ビツト位置を表わ
す）の論理積が出側上り多重伝送路２−２の同じ
チヤネル番号の信号として得られる。但し、加入
者伝送路フレームのフレーム同期ビツトに相当す
るビツトは常に“１”となるようにする。 Reading from the elastic store 23 is as follows:
The bit synchronization signal c generated by the clock extraction circuit 15 is read out using the frame synchronization signal d from the frame extraction circuit 17. As a result, frame synchronization is achieved between the two inputs of the AND gate 24, that is, the signal b of the multiplex transmission line and the signal n of the subscriber transmission line (which is equal to the signal i when there is no fault), and therefore the output of the AND gate 24 Signal j includes an incoming upstream multiplex transmission line 2-1 and an upstream subscriber transmission line 7.
The AND of the signals having the same channel number (the channel number represents the signal bit position within one frame) is obtained as the signal having the same channel number on the output upstream multiplex transmission path 2-2. However, the bit corresponding to the frame synchronization bit of the subscriber transmission line frame is always set to "1".

論理積ゲート２４の出力信号ｊには入力信号ｂ
と信号ｎのタイミングのずれによるハザードが発
生するため、クロツク抽出回路１５のビツト同期
信号ｋを用いてＤ形FF回路２５により波形整形
を行ない、その出力信号ｌをバツフア増幅器２６
により出側上り多重伝送路２−２に送信する。 The output signal j of the AND gate 24 has the input signal b.
Since a hazard occurs due to a timing difference between the clock signal and the signal n, the waveform is shaped by the D-type FF circuit 25 using the bit synchronization signal k of the clock extraction circuit 15, and the output signal l is sent to the buffer amplifier 26.
is transmitted to the outgoing uplink multiplex transmission path 2-2.

分岐挿入装置の加入者伝送路終端回路は受信バ
ツフア増幅器１９及び伝送路終端抵抗１８により
構成し、上り加入者伝送路７が開放又は短絡した
時には規定の論理値“１”を出力する構成とす
る。（受信バツフア増幅器１９としては、例えば、
テキサス・インスツルメント社のラインレシーバ
ー用のIC、SN75124が知られている。） 状態遷移検出回路２７は、例えばカウンタある
いは単安定マルチバイブレータ等を用いて構成
し、信号ｅの状態遷移が一定時間t1以上存在しな
いことを検出すると信号ｍを論理値“１”とし、
その後、信号ｅの状態遷移が始まり、一定時間t2
以上続いたことを検出すると信号ｍを論理値
“０”にするようにする。すなわち、状態遷移検
出回路２７と論理和ゲート２８の作用により、信
号ｅの状態遷移が一定時間以上在存しない場合に
エラステイツクストア２３の出力を強制的に論理
値“１”にする。 The subscriber transmission line terminating circuit of the add-drop device is composed of a receiving buffer amplifier 19 and a transmission line terminating resistor 18, and is configured to output a prescribed logical value "1" when the upstream subscriber transmission line 7 is open or short-circuited. . (For example, as the receiving buffer amplifier 19,
Texas Instruments' line receiver IC, SN75124, is well known. ) The state transition detection circuit 27 is configured using, for example, a counter or a monostable multivibrator, and when it detects that the state transition of the signal e does not exist for a certain period of time t1 or more, it sets the signal m to a logical value "1",
After that, the state transition of the signal e begins, and a certain period of time t 2
When it is detected that the above continues, the signal m is set to the logical value "0". That is, by the action of the state transition detection circuit 27 and the OR gate 28, the output of the elastic store 23 is forcibly set to the logical value "1" when there is no state transition of the signal e for a certain period of time or more.

ここで、伝送路終端抵抗１８から論理和ゲート
２８に至るまでの各部１９，２０，２１，２２，
２３，２７を、各端末毎に設置すれば、本装置は
複数の端末を収容することができる。 Here, each part 19, 20, 21, 22, from the transmission line terminating resistor 18 to the OR gate 28,
23 and 27 are installed for each terminal, this device can accommodate a plurality of terminals.

以上の構成において、多重伝送路と加入者伝送
路の無通話チヤネルのビツトパタンは前記のよう
に全て“１”としているため、端末が多重伝送路
の空きチヤネルの使用権を獲得し、そのチヤネル
番号と同じ加入者伝送路のチヤネルに信号を送出
することにより、端末の信号が多重伝送路の該当
するチヤネルに出力として得られ、入り側上り多
重伝送路２−１の信号、すなわち、他の端末等が
使用しているチヤネルの信号は全て出側上り多重
伝送路２−２に送出され挿入が行なわれる。 In the above configuration, since the bit patterns of the idle channels of the multiplex transmission path and the subscriber transmission path are all "1" as described above, the terminal acquires the right to use an empty channel of the multiplex transmission path and assigns the channel number. By sending a signal to the channel of the same subscriber transmission path, the signal of the terminal is obtained as an output to the corresponding channel of the multiplex transmission path, and the signal of the incoming uplink multiplex transmission path 2-1, that is, the signal of the other terminal All the signals of the channels used by the above are sent to the outgoing uplink multiplex transmission path 2-2 and inserted.

次に障害時の動作について説明する。端末が障
害で自端末を上り加入者伝送路７から切り離した
場合、また上り加入者伝送路７に切断、短絡等の
障害（瞬断等も含む）が発生した場合には受信バ
ツフア増幅器１９の出力信号ｅは論理値“１”と
なつてクロツク抽出回路２０は自走する。従つ
て、エラステイツクストア２３へは入り側上り多
重伝送路２−１の周期とは異なる周期で論理値
“１”の信号が書き込まれることになるが、書き
込まれる信号は全て論理値１であるため、入り側
上り多重伝送路２−１の周期で読み出される信号
ｉ，ｎも全て論理値“１”となり、入り側上り多
重伝送路２−１上の信号は全て論理積ゲート２４
を通過し、出側上り多重伝送路２−２に送出さ
れ、入り側上り多重伝送路２−１上の信号は端末
又は上り加入者伝送路７の障害の影響を受けな
い。 Next, the operation at the time of failure will be explained. If a terminal disconnects itself from the uplink subscriber transmission line 7 due to a failure, or if a failure such as a disconnection or short circuit (including momentary interruption, etc.) occurs in the uplink subscriber transmission line 7, the reception buffer amplifier 19 The output signal e has a logical value of "1" and the clock extraction circuit 20 runs free. Therefore, signals with a logic value of "1" are written to the elastic store 23 at a cycle different from the cycle of the incoming uplink multiplex transmission line 2-1, but all the signals written are at a logic value of 1. Therefore, the signals i and n read out at the cycle of the input side uplink multiplex transmission line 2-1 also all have a logic value of "1," and all the signals on the input side uplink multiplex transmission line 2-1 are output to the AND gate 24.
The signal on the incoming uplink multiplex transmission line 2-1 is not affected by a failure in the terminal or the uplink subscriber transmission line 7.

一方、障害から復旧する場合には、クロツク抽
出回路２０が障害中に自走するため、クロツク信
号ｇの位相がずれ、第４図のＸ点に示すようにＤ
形FF回路２１が誤つた論理値を波形再生して信
号ｆの如き波形になる可能性がある。また障害中
に信号ｅが論理値“１”をとり続けるため、フレ
ーム抽出回路２２のフレーム同期がはずれ、障害
復旧後、誤つた信号をエラステイツクストア２３
に書き込む可能性もある。しかしこれらの場合、
状態遷移検出回路２７が信号ｍを論理値“１”と
することにより、信号ｎを論理値“１”とし、そ
の結果論理積ゲート２４において誤つた信号が挿
入されることをなくすことができる。この動作を
行なうための前記時間t1、t2の条件としては、例
えば、クロツク抽出回路２０が自走してクロツク
信号ｇの位相のずれが許容値を越えるまでの時
間、または信号ｅが論理値“１”をとり続けてフ
レーム抽出回路２２のフレーム同期がはずれるま
での時間のどちらか小さい方をt1とし、障害復旧
後クロツク信号ｇの位相のずれが許容値内に戻る
までの時間、またはフレーム抽出回路２２がフレ
ーム同期をとりなおすのに要する時間のどちらか
大きい方をt2とする。 On the other hand, when recovering from a fault, the clock extraction circuit 20 runs free during the fault, so the phase of the clock signal g shifts, resulting in D as shown at point X in FIG.
There is a possibility that the FF circuit 21 reproduces the waveform of the erroneous logical value, resulting in a waveform like the signal f. In addition, since the signal e continues to take the logical value "1" during the fault, the frame extraction circuit 22 loses frame synchronization, and after the fault is recovered, the erroneous signal is transferred to the elastic store 23.
It is also possible to write to. But in these cases,
The state transition detection circuit 27 sets the signal m to the logic value "1", thereby setting the signal n to the logic value "1", and as a result, it is possible to prevent the AND gate 24 from inserting an erroneous signal. The conditions for the times t 1 and t 2 for performing this operation include, for example, the time until the clock extraction circuit 20 runs free and the phase shift of the clock signal g exceeds an allowable value, or the time until the clock signal e reaches a logic level. The smaller of the time from when the value continues to be "1" until the frame extraction circuit 22 loses frame synchronization is defined as t1 , and the time until the phase shift of the clock signal g returns to within the allowable value after the failure is recovered. or the time required for the frame extraction circuit 22 to re-establish frame synchronization, whichever is greater, is defined as t2 .

なお、信号ｃおよびｌは第３図に示した波形ｃ
およびｌと同一であり、信号ｅ，ｇとは任意の位
相関係にある。 Note that the signals c and l have the waveform c shown in FIG.
and l, and have an arbitrary phase relationship with the signals e and g.

また、以上の説明において論理値“１”論理値
“０”に、論理値“０”を論理値“１”に、論理
積を論理和に、論理和を論理積に変更しても同一
の作用をすることは言うまでもない。 Also, in the above explanation, even if you change the logical value "1" to the logical value "0", the logical value "0" to the logical value "1", the logical product to the logical sum, and the logical sum to the logical product, the same result will occur. Needless to say, it works.

以上説明したように、本発明の多重加入者系分
岐挿入装置によれば、端末の障害、加入者伝送路
の障害が多重伝送路に波及せず、特に障害から復
旧する時に生じやすい誤動作をも完全に救済する
ことができるため、高い信頼性を有する多重加入
者系を構成することが可能となる。 As explained above, according to the multiple subscriber add/drop device of the present invention, terminal failures and subscriber transmission path failures do not spread to the multiplex transmission path, and malfunctions that are particularly likely to occur when recovering from a failure can be avoided. Since complete recovery is possible, it is possible to construct a multi-subscriber system with high reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明を用いた多重加入者系のシステ
ム構成を示す一実施例図、第２図は第１図におけ
る本発明による分岐挿入装置の詳細な構成を示す
一実施例図、第３図は第２図に示した本発明によ
る分岐挿入装置の各部における信号の一例を示す
図、第４図は第２図に示した本発明による分岐挿
入装置の各部における信号の障害時の一例を示す
図である。 １……加入者系交換機、２……上り多重伝送
路、３……下り多重伝送路、４……端末、５……
伝送路終端装置、６……分岐挿入装置、７……上
り加入者伝送路、８……下り加入者伝送路、９，
１４，１９……受信バツフア増幅器、１０，１
５，２０……クロツク抽出回路、１１，１６，２
１，２５……Ｄ形FF回路、１２，１３，２６…
…送信バツフア増幅器、１７，２２……フレーム
抽出回路、１８……伝送路終端抵抗、２３……エ
ラステイツクストア、２４……論理積ゲート、２
７……状態遷移検出回路、２８……論理和ゲー
ト。 FIG. 1 is an embodiment diagram showing the system configuration of a multiple subscriber system using the present invention, FIG. The figure shows an example of signals in each part of the add/drop multiplexer according to the present invention shown in FIG. 2, and FIG. FIG. 1...Subscriber system exchange, 2...Uplink multiplex transmission line, 3...Downlink multiplex transmission line, 4...Terminal, 5...
Transmission line termination device, 6... Add/drop device, 7... Uplink subscriber transmission line, 8... Downlink subscriber transmission line, 9,
14, 19...Reception buffer amplifier, 10, 1
5, 20...Clock extraction circuit, 11, 16, 2
1, 25...D type FF circuit, 12, 13, 26...
... Transmission buffer amplifier, 17, 22 ... Frame extraction circuit, 18 ... Transmission line termination resistor, 23 ... Elastic store, 24 ... AND gate, 2
7... State transition detection circuit, 28... OR gate.

Claims (1)

【特許請求の範囲】[Claims] １ 複数の端末を分岐挿入装置を介してデイジタ
ル化した多重伝送路に時分割多重で収容し、上記
多重伝送路及び端末から分岐挿入装置までの伝送
路の無通話チヤネルのビツトパタンを全て論理値
“１”または“０”の予め定めた一方とし、上記
分岐挿入装置の挿入回路を前記予め定めた一方が
論理値“１”または“０”であるときに対応して
論理積ゲートまたは論理和ゲートで構成し、その
分岐挿入装置の端末側挿入部にエラステイツクス
トアを用いたフレーム同期化回路を設け、上記端
末から分岐挿入装置までの伝送路が開放状態とな
つた時、その分岐挿入装置の端末側挿入部の入力
を強制的に論理値“１”または“０”の前記予め
定めた一方にする伝送路終端回路を設け、更に上
記端末から分岐挿入装置までの伝送路上の信号の
状態遷移が一定時間以上存在しない場合に上記エ
ラステイツクストアの出力を強制的に論理値
“１”または“０”の前記予め定めた一方にする
回路を設けることを特徴とする多重加入者系分岐
挿入装置。1 A plurality of terminals are accommodated in a multiplex transmission path digitized via a drop/drop/add device by time division multiplexing, and the bit patterns of the silent channels of the multiplex transmission path and the transmission path from the terminal to the add/drop device are all set to logical values “ When the predetermined value is "1" or "0", the insertion circuit of the add/drop device is configured to operate an AND gate or a OR gate in response to the case where the predetermined value is "1" or "0". A frame synchronization circuit using an elastic store is installed in the terminal-side insertion section of the add-drop multiplexer, and when the transmission path from the terminal to the add-drop multiplexer becomes open, the A transmission line termination circuit is provided that forces the input of the terminal-side insertion unit to be one of the predetermined logic values "1" or "0", and furthermore, the state transition of the signal on the transmission line from the terminal to the add-drop device is provided. A multi-subscriber branch/add device, characterized in that a circuit is provided for forcing the output of the elastic store to be one of the predetermined logic values "1" or "0" when the elastic store does not exist for a certain period of time or more. .
JP10388283A 1983-06-10 1983-06-10 Multiple subscriber system branching and inserting device Granted JPS59229943A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10388283A JPS59229943A (en) 1983-06-10 1983-06-10 Multiple subscriber system branching and inserting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10388283A JPS59229943A (en) 1983-06-10 1983-06-10 Multiple subscriber system branching and inserting device

Publications (2)

Publication Number Publication Date
JPS59229943A JPS59229943A (en) 1984-12-24
JPH0126576B2 true JPH0126576B2 (en) 1989-05-24

Family

ID=14365800

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10388283A Granted JPS59229943A (en) 1983-06-10 1983-06-10 Multiple subscriber system branching and inserting device

Country Status (1)

Country Link
JP (1) JPS59229943A (en)

Also Published As

Publication number Publication date
JPS59229943A (en) 1984-12-24

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