JPH0225581B2 - - Google Patents
Info
- Publication number
- JPH0225581B2 JPH0225581B2 JP56081580A JP8158081A JPH0225581B2 JP H0225581 B2 JPH0225581 B2 JP H0225581B2 JP 56081580 A JP56081580 A JP 56081580A JP 8158081 A JP8158081 A JP 8158081A JP H0225581 B2 JPH0225581 B2 JP H0225581B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- station
- timing
- timing signal
- synchronization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/20—Repeater circuits; Relay circuits
- H04L25/24—Relay circuits using discharge tubes or semiconductor devices
- H04L25/242—Relay circuits using discharge tubes or semiconductor devices with retiming
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はPCM通信方式の従属同期中継方式に
関する。特に、一方の端局である主局に基準タイ
ミング信号発生回路を備え、他方の端局である従
局は主局から伝送路を通じて受信されるタイミン
グ信号に同期して動作するように構成された従属
同期方式の中継方式に使用する中継器の構成に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dependent synchronous relay system of a PCM communication system. In particular, one terminal station, the master station, is equipped with a reference timing signal generation circuit, and the other terminal station, the slave station, is configured to operate in synchronization with a timing signal received from the master station through a transmission path. The present invention relates to the configuration of a repeater used in a synchronous relay method.
第1図は従属同期方式によるPCM中継方式の
原理を示す説明図である。すなわち、主局1と従
局2との間に、主局1から従局2に向けて信号が
伝送される下り回線3と、従局2から主局1に向
けて信号が伝送される上り回線4とにより接続さ
れ、その回線3および4に、途中に生じる信号の
減衰を再生中継する再生中継器5を配置して中継
方式が構成される。再生中継器5は回線3,4の
長さに応じて複数個挿入されるが、第1図ではそ
の1個のみを表示する。
FIG. 1 is an explanatory diagram showing the principle of a PCM relay system using a dependent synchronization system. That is, between the master station 1 and the slave station 2, there is a downlink 3 through which signals are transmitted from the master station 1 to the slave station 2, and an uplink 4 through which signals are transmitted from the slave station 2 to the master station 1. A relay system is constructed by arranging a regenerative repeater 5 on the lines 3 and 4, which regenerates and repeats signal attenuation that occurs on the way. A plurality of regenerative repeaters 5 are inserted depending on the lengths of the lines 3 and 4, but only one of them is shown in FIG.
この中継方式の一方の端局である主局1には基
準タイミング信号発生回路8を備え、この回路8
の発生するタイミング信号に同期して、送信回路
9から信号が下り回線3に送信される。他方の端
局である従局2では、この下り回線3から受信さ
れる信号を等化回路10で等化増幅し、その出力
からタイミング抽出回路11により、タイミング
信号を抽出する。このタイミング抽出回路11に
より抽出されたタイミング信号に同期して、送信
回線12が上り回線4に信号を送信する。 The main station 1, which is one terminal station of this relay system, is equipped with a reference timing signal generation circuit 8.
A signal is transmitted from the transmitting circuit 9 to the downlink 3 in synchronization with the timing signal generated by the transmitting circuit 9. In the slave station 2, which is the other terminal station, the signal received from the downlink 3 is equalized and amplified by an equalization circuit 10, and a timing signal is extracted from the output by a timing extraction circuit 11. The transmission line 12 transmits a signal to the uplink line 4 in synchronization with the timing signal extracted by the timing extraction circuit 11.
上り回路4から主局1に到達した信号は、等化
回路15により等化増幅され、その出力信号から
タイミング抽出回路16により、タイミング信号
が抽出される。等化回路15の出力はこのタイミ
ング信号に同期して、エラステイツクメモリ17
に書込まれ、さらに基準タイミング発生回路8の
出力タイミング信号に同期して、エラステイツク
メモリ17からその書込まれた信号が読出され
る。 The signal reaching the main station 1 from the upstream circuit 4 is equalized and amplified by the equalization circuit 15, and a timing signal is extracted from the output signal by the timing extraction circuit 16. The output of the equalization circuit 15 is sent to the elastic memory 17 in synchronization with this timing signal.
Further, in synchronization with the output timing signal of the reference timing generation circuit 8, the written signal is read out from the elastic memory 17.
第2図は従来例方式の再生中継器の構成図であ
る。すなわち、各再生中継器5では、それぞれ回
線3,4の信号を等化回路20,21で等化増幅
し、その出力からそれぞれタイミング抽出回路2
2,23によりタイミング信号を抽出し、それぞ
れこのタイミング信号に同期して送信回路24,
25から信号を送信するように構成されている。 FIG. 2 is a block diagram of a conventional regenerative repeater. That is, in each regenerative repeater 5, the signals of the lines 3 and 4 are equalized and amplified by the equalization circuits 20 and 21, and the timing extraction circuit 2 is used from the output thereof.
2 and 23, and the transmitting circuits 24 and 23 respectively synchronize with this timing signal.
The device is configured to transmit signals from 25.
このような従属同期方式は、従局2に基準タイ
ミング発生回路を備える必要がないので安価にな
る利点があるが、タイミング信号が各再生中継器
5で繰返して抽出され再生されるため、これに伴
うジツタが次第に累加される欠点がある。従つて
再生中継器が多数個必要とされる回線には、従局
同期方式を利用することができない。
Such a slave synchronization method has the advantage of being inexpensive since it is not necessary to equip the slave station 2 with a reference timing generation circuit, but since the timing signal is repeatedly extracted and reproduced by each regenerative repeater 5, the accompanying There is a drawback that jitters gradually accumulate. Therefore, the slave station synchronization method cannot be used for lines that require a large number of regenerative repeaters.
本発明はこれを改良するもので、従属同期方式
で再生中継に伴い累加されるジツタを小さく抑圧
することを目的とする。 The present invention aims to improve this problem, and aims to suppress the jitter that is accumulated during regenerative relay using the dependent synchronization method.
本発明は、従属同期方式の主局と従局との間に
挿入される再生中継器にエラステイツクメモリを
設けて、上り回線の信号のタイミングを下り回線
にあるジツタの少ないタイミング信号に同期させ
て読み出して信号を伝送することを特徴とする。
The present invention provides an elastic memory in a regenerative repeater inserted between a master station and a slave station in a slave synchronization system, and synchronizes the timing of an uplink signal with a timing signal with less jitter in a downlink. It is characterized by reading and transmitting signals.
第3図は本発明実施例装置のブロツク構成図で
ある。これは第1図に示す再生中継器5にそつく
り入れ替えて用いることができ、本発明を実施す
ることにより両端局には変更がない。本発明実施
例の再生中継器5は、下り回線3については、等
化回路20、タイミング抽出回路22および送信
回路24とも、第2図に示す従来例装置と変りは
ないが、上り回線4については、等化回路21の
出力にエラステイツクメモリ27を挿入し、この
エラステイツクメモリ27には、タイミング回路
23により抽出されるタイミング信号に同期して
書込を行い、下り回線3のタイミング信号22の
抽出するタイミング信号に同期して読出を行うと
ころに特徴がある。
FIG. 3 is a block diagram of an apparatus according to an embodiment of the present invention. This can be used in place of the regenerative repeater 5 shown in FIG. 1, and by implementing the present invention, there is no change in both terminal stations. The regenerative repeater 5 according to the embodiment of the present invention has the same equalization circuit 20, timing extraction circuit 22, and transmission circuit 24 for the downlink 3 as the conventional device shown in FIG. 2, but for the uplink 4. In this example, an elastic memory 27 is inserted into the output of the equalization circuit 21, and writing is performed in this elastic memory 27 in synchronization with the timing signal extracted by the timing circuit 23. The feature is that the reading is performed in synchronization with the timing signal extracted by.
すなわち、上り回線4の信号は等化回路21で
等化増幅された後、その信号のタイミングでエラ
ステイツクメモリ27に書込まれる。この上り回
線4のタイミングは、第1図でわかるように従局
2で折返し再生されてきたものであるので、下り
回線3のタイミングに比べると再生中継された回
数が多く、累加されたジツタの量も大きい。エラ
ステイツクメモリ27に書込まれた信号は、ジツ
タの少ない下り回線3から抽出されたタイミング
信号に同期して読出されることにより、ジツタが
小さくなる。この信号は送信回路25からさらに
上り回線に送出される。 That is, after the signal on the uplink 4 is equalized and amplified by the equalization circuit 21, it is written into the elastic memory 27 at the timing of the signal. As can be seen in Fig. 1, the timing of this uplink 4 is the one that has been replayed back by the slave station 2, so compared to the timing of the downlink 3, it has been replayed more times and the amount of accumulated jitter is higher. It's also big. The signal written in the elastic memory 27 has less jitter because it is read out in synchronization with the timing signal extracted from the downlink 3 with less jitter. This signal is further sent out from the transmitting circuit 25 to the uplink.
このように構成された再生中継器5を、主局1
と従局2との間の回線のほぼ中間位置の中継器に
1個所だけ使用すると、累加されるジツタは、こ
の再生中継器5の上り回線入力または主局1の上
り回線入力でほぼ最大となるが、その大きさは従
来方式に比べると約2分の1になる。 The regenerative repeater 5 configured in this way is connected to the main station 1.
If only one repeater is used at a repeater located approximately in the middle of the line between the regenerative repeater 5 and the slave station 2, the cumulative jitter will be almost at its maximum at the uplink input of this regenerative repeater 5 or the uplink input of the main station 1. However, the size is about half that of the conventional method.
本発明の再生中継器は回線の主局と従局との中
間位置の1個所に限らず、複数の個所に使用する
ことができる。 The regenerative repeater of the present invention is not limited to one location between the main station and the slave station of the line, but can be used at a plurality of locations.
以上述べたように、本発明により従属同期方式
をとるPCM中継方式で、伝送路の再生中継によ
り生ずるジツタの累加を小さく抑えることができ
る。特に主局と従局との中間位置でジツタの少な
い下り回線の送信タイミング信号を用いると、従
局から主局への信号伝送におけるタイミング信号
のジツタを小さくできる。
As described above, according to the present invention, the accumulation of jitter caused by regenerative relaying of a transmission path can be suppressed to a small level using a PCM relaying system that uses a dependent synchronization system. In particular, if a downlink transmission timing signal with less jitter is used at an intermediate position between the master station and the slave station, the jitter in the timing signal during signal transmission from the slave station to the master station can be reduced.
これにより信号の誤りを小さくでき、長距離の
方式に経済的な従属同期方式を適用することがで
きる。 As a result, signal errors can be reduced, and an economical dependent synchronization method can be applied to long-distance systems.
第1図は従属同期方式の説明図。第2図は従来
例装置の構成図。第3図は本発明実施例装置の構
成図。
1……主局、2……従局、3……下り回線、4
……上り回線、5……再生中継器、8……基準タ
イミング信号発生回路、9……送信回路、10…
…等化回路、11……タイミング抽出回路、12
……送信回路、15……等化回路、16……タイ
ミング抽出回路、17……エラステイツクメモ
リ、20,21……等化回路、22,23……タ
イミング抽出回路、24,25……送信回路、5
7……エラステイツクメモリ。
FIG. 1 is an explanatory diagram of the dependent synchronization method. FIG. 2 is a configuration diagram of a conventional device. FIG. 3 is a configuration diagram of an apparatus according to an embodiment of the present invention. 1...Main station, 2...Slave station, 3...Down line, 4
...Uplink, 5...Regenerative repeater, 8...Reference timing signal generation circuit, 9...Transmission circuit, 10...
... Equalization circuit, 11 ... Timing extraction circuit, 12
... Transmission circuit, 15 ... Equalization circuit, 16 ... Timing extraction circuit, 17 ... Elastic memory, 20, 21 ... Equalization circuit, 22, 23 ... Timing extraction circuit, 24, 25 ... Transmission circuit, 5
7...Elastic memory.
Claims (1)
回路が発生するタイミング信号に同期して従局に
対して信号を伝送する手段とを備え、 従局に前記主局からのタイミング信号を受信す
る手段と、前記タイミング信号に同期して前記主
局に信号を伝送する手段とを備え、 前記主局と前記従局との間の伝送路に複数の再
生中継器が挿入された 従属同期通信方式において、 上記再生中継器内の少なくとも上記主局と従局
の中間に位置する再生中継器は、 前記主局から前記従局に向けて信号が伝送され
る下り回線からタイミング信号を抽出する第一の
タイミング抽出回路と、 前記従局から前記主局へ向けて信号が伝送され
る上り回線からタイミング信号を抽出する第二の
タイミング抽出回路と、 前記上り回線に挿入され前記第二のタイミング
抽出回路の出力タイミング信号に同期して伝送信
号の書込を行い前記第一のタイミング抽出回路の
出力タイミング信号に同期して伝送信号の読出し
を行うエラステイツクメモリと を備えたことを特徴とする従属同期中継方式。[Claims] 1. A master station includes a reference timing signal generation circuit, and means for transmitting a signal to a slave station in synchronization with a timing signal generated by this circuit, and the slave station receives a timing signal from the master station. and means for transmitting a signal to the master station in synchronization with the timing signal, and a plurality of regenerative repeaters are inserted in a transmission path between the master station and the slave station. In the communication system, the regenerative repeater located at least between the main station and the slave station in the regenerative repeater includes a first regenerative repeater that extracts a timing signal from a downlink through which a signal is transmitted from the master station to the slave station. a second timing extraction circuit that extracts a timing signal from an uplink through which signals are transmitted from the slave station to the main station; and a second timing extraction circuit that is inserted into the uplink. A dependent synchronous relay comprising an elastic memory that writes a transmission signal in synchronization with the output timing signal and reads the transmission signal in synchronization with the output timing signal of the first timing extraction circuit. method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56081580A JPS57194653A (en) | 1981-05-27 | 1981-05-27 | Reproducing repeater |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56081580A JPS57194653A (en) | 1981-05-27 | 1981-05-27 | Reproducing repeater |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57194653A JPS57194653A (en) | 1982-11-30 |
| JPH0225581B2 true JPH0225581B2 (en) | 1990-06-04 |
Family
ID=13750245
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56081580A Granted JPS57194653A (en) | 1981-05-27 | 1981-05-27 | Reproducing repeater |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57194653A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3434869B2 (en) * | 1994-02-07 | 2003-08-11 | 株式会社日立製作所 | Optical regenerative repeater and optical transmission device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49121463A (en) * | 1973-03-20 | 1974-11-20 | ||
| JPS5941336B2 (en) * | 1976-07-21 | 1984-10-06 | 日本電気株式会社 | buffer memory device |
-
1981
- 1981-05-27 JP JP56081580A patent/JPS57194653A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57194653A (en) | 1982-11-30 |
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